
Rev.2.40 Jun 14, 2004 page 36 of 56
38C1 Group
Fig. 35 Structure of clock output control register
OTHER FUNCTION REGISTERS
● φ clock output function
The internal clock φ can be output from port P6
3 by setting the φ
output control register.
At φ clock output, set “1” to the bit 3 of the port P6 direction regis-
ter.
b
7b
0
φ output control register
(CKOUT: address 002A
16
, initial value: 00
16
)
φ output control bit
00:
01:
10:
11:
P
o
r
t
f
u
n
c
t
i
o
n
φ
fr
e
q
u
e
n
c
y
s
i
g
n
a
l
o
u
t
p
u
t
X
C
I
N
f
r
e
q
u
e
n
c
y
s
i
g
n
a
l
o
u
t
p
u
t
N
o
t
a
v
a
i
l
a
b
l
e
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
(
D
o
n
o
t
w
r
i
t
e
“
1
”
t
o
t
h
i
s
b
i
t
)
b7 b0
DB
0
data stored
DB
1
data stored
DB
2
data stored
DB
3
data stored
DB
4
data stored
DB
5
data stored
DB
6
data stored
DB
7
data stored
b
7b0
RRF register
(RRFR: address 002F
16
, initial value: 00
16
)
D
B
4
d
a
t
a
s
t
o
r
e
d
D
B
5
d
a
t
a
s
t
o
r
e
d
D
B
6
d
a
t
a
s
t
o
r
e
d
D
B
7
d
a
t
a
s
t
o
r
e
d
D
B
0
d
a
t
a
s
t
o
r
e
d
D
B
1
d
a
t
a
s
t
o
r
e
d
D
B
2
d
a
t
a
s
t
o
r
e
d
D
B
3
d
a
t
a
s
t
o
r
e
d
Temporary data registers 0, 1, 2
(TD
0
, TD
1
, TD
2
: address 002C
16
, 002D
16
, 002E
16
,
initial value: 00
16
)
● Temporary data register
The temporary data register (addresses 002C16 to 002E16) is the
8-bit register and does not have the control function. It can be
used to store data temporarily. It is initialized after reset.
● RRF register
The RRF register (address 002F16) is the 8-bit register and does
not have the control function.
As for the value written in this register, high-order 4 bits and low-
order 4 bits interchange.
It is initialized after reset.
Fig. 36 Structure of temporary data register, RRF register
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