Renesas HD151TS207SS Uživatelský manuál stáhnout pdf

Rev.1.00, Apr.25.2003, page 1 of 38

HD151TS207SS

Mother Board Clock Generator

for Intel P4+ Chipset (Springdale)

REJ03D0006-0100Z

Preliminary

Rev.1.00

Apr.25.2003

Description

The HD151TS207SS is Intel CK409T type high-performance, low-skew, low-jitter, PC motherboard clock

generator. It is specifically designed for Intel Pentium

4+ chipset.

Features

• 3 differential pairs of current mode control CPU clocks

• 1 differential pair of Serial Reference Clock (SRC), selectable 100 MHz/200 MHz

• 6 copies PCI clocks and 3 copies PCIF clocks @3.3V, 33.3 MHz

• 1 copy PCI clock @3.3 V, selectable 33.3 MHz/25 MHz

• 1 copy USB clock @3.3 V, selectable 48 MHz/24 MHz

• 1 copy DOT clock @3.3 V, 48 MHz

• 4 copies of 3V66 clocks @3.3 V, 66.6 MHz

• 1 copy of 3V66/VCH clock @3.3 V, selectable 66.6 MHz/48 MHz

• 2 copies of REF clocks @3.3 V, 14.318 MHz

• Power save and clock stop function

• I

serial port programming

• Programmable Clock Control (Spread Spectrum Percentage, Clock Output Skew, Slew Rate)

• Watchdog timer and reset output

• 56pin SSOP (300 mils)

Note: I

C is a trademark of Philips Corporation.

Pentium is registered trademark of Intel Corporation

1 2 3 4 5 6 ... 37 38

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Strany 1 - HD151TS207SS

Rev.1.00, Apr.25.2003, page 1 of 38HD151TS207SSMother Board Clock Generatorfor Intel P4+ Chipset (Springdale)REJ03D0006-0100ZPreliminaryRev.1.00Apr.

Strany 2 - Key Specifications

HD151TS207SSRev.1.00, Apr.25.2003, page 10 of 38I2C Controlled Register Bit Map (cont.)Byte4 Control RegisterBit Description Contents Type Default N

Strany 3 - Pin Arrangement

HD151TS207SSRev.1.00, Apr.25.2003, page 11 of 38I2C Controlled Register Bit Map (cont.)Byte7 Vendor Identification RegisterBit Description Contents

Strany 4 - Pin Descriptions

HD151TS207SSRev.1.00, Apr.25.2003, page 12 of 38I2C Controlled Register Bit Map (cont.)Byte9 Control RegisterBit Description Contents Type Default N

Strany 5 - Pin Descriptions (cont.)

HD151TS207SSRev.1.00, Apr.25.2003, page 13 of 38I2C Controlled Register Bit Map (cont.)Table6 Clock Frequency Function TableFS_4 FS_3 FS_2 FS_A FS_B

Strany 6 - Block Diagram

HD151TS207SSRev.1.00, Apr.25.2003, page 14 of 38I2C Controlled Register Bit Map (cont.)Byte10 Control RegisterBit Description Contents Type Default

Strany 7 - C Controlled Register Bit Map

HD151TS207SSRev.1.00, Apr.25.2003, page 15 of 38I2C Controlled Register Bit Map (cont.)Byte12 Control RegisterBit Description Contents Type Default

Strany 8 - Byte2 Control Register

HD151TS207SSRev.1.00, Apr.25.2003, page 16 of 38I2C Controlled Register Bit Map (cont.)Byte14 Control RegisterBit Description Contents Type Default

Strany 9 - Byte3 Control Register

HD151TS207SSRev.1.00, Apr.25.2003, page 17 of 38I2C Controlled Register Bit Map (cont.)Byte16 Control RegisterBit Description Contents Type Default

Strany 10 - Byte6 Control Register

HD151TS207SSRev.1.00, Apr.25.2003, page 18 of 38I2C Controlled Register Bit Map (cont.)Byte18 Control RegisterBit Description Contents Type Default

Strany 11

HD151TS207SSRev.1.00, Apr.25.2003, page 19 of 38I2C Controlled Register Bit Map (cont.)Byte19 Control RegisterBit Description Contents Type Default

Strany 12 - Byte9 Control Register

HD151TS207SSRev.1.00, Apr.25.2003, page 2 of 38Key Specifications• Supply Voltages: VDD = 3.3 V±5%• CPU clock cycle to cycle jitter = |125ps| (SSC

Strany 13

HD151TS207SSRev.1.00, Apr.25.2003, page 20 of 38I2C Controlled Register Bit Map (cont.)Byte22 Control RegisterBit Description Contents Type Default

Strany 14 - Byte11 Control Register

HD151TS207SSRev.1.00, Apr.25.2003, page 21 of 38I2C Controlled Register Bit Map (cont.)Byte24 Control RegisterBit Description Contents Type Default

Strany 15 - Byte13 Control Register

HD151TS207SSRev.1.00, Apr.25.2003, page 22 of 38I2C Controlled Register Bit Map (cont.)Byte26 Control RegisterBit Description Contents Type Default

Strany 16 - Byte15 Control Register

HD151TS207SSRev.1.00, Apr.25.2003, page 23 of 38I2C Controlled Register Bit Map (cont.)Byte28 Control RegisterBit Description Contents Type Default

Strany 17 - Byte17 Control Register

HD151TS207SSRev.1.00, Apr.25.2003, page 24 of 38Clock Stop Timing Diagram6× Iref (Controled by Byte2[6])2× Iref (Controled by Byte2[5:3])Tristate (C

Strany 18 - Byte18 Control Register

HD151TS207SSRev.1.00, Apr.25.2003, page 25 of 38Renesas clock generator I2C Serial Interface Operation1. Write mode1.1 Controller (host) sends a sta

Strany 19 - Byte21 Control Register

HD151TS207SSRev.1.00, Apr.25.2003, page 26 of 38Renesas clock generator I2C Serial Interface Operation (cont.)2. Read mode2.1 Controller (host) send

Strany 20 - Byte23 Control Register

HD151TS207SSRev.1.00, Apr.25.2003, page 27 of 38Absolute Maximum RatingsItem Symbol Ratings Unit ConditionsSupply voltage VDD –0.5 to 4.6 VInput vol

Strany 21 - Byte25 Control Register

HD151TS207SSRev.1.00, Apr.25.2003, page 28 of 38DC Electrical Characteristics / Serial Input PortTa = 0°C to 70°C, VDD = 3.3 VItem Symbol Min Typ *1

Strany 22 - Byte27 Control Register

HD151TS207SSRev.1.00, Apr.25.2003, page 29 of 38DC Electrical Characteristics CPU/CPU# ClockTa = 0°C to 70°C, VDD = 3.3 V, Iref = 475 ΩItem Symbol M

Strany 23 - Byte29 Control Register

HD151TS207SSRev.1.00, Apr.25.2003, page 3 of 38Pin Arrangement12345678910REF0REF1VDD_REFXTAL_INXTAL_OUTVSS_REFFS2/PCIF_0FS4/PCIF_1VDD_PCIVSS_PCIPCI_

Strany 24 - Clock Stop Timing Diagram

HD151TS207SSRev.1.00, Apr.25.2003, page 30 of 38DC Electrical Characteristics SRC/SRC# ClockTa = 0°C to 70°C, VDD = 3.3 V, Iref = 475 ΩItem Symbol M

Strany 25 - C Serial Interface Operation

HD151TS207SSRev.1.00, Apr.25.2003, page 31 of 38DC Electrical Characteristics / 3V66 Buffer (CK409T Type5 Buffer)Ta = 0°C to 70°C, VDD = 3.3 VItem S

Strany 26

HD151TS207SSRev.1.00, Apr.25.2003, page 32 of 38DC Electrical Characteristics / PCI & PCIF Clock (CK409T Type5 Buffer)Ta = 0°C to 70°C, VDD = 3.

Strany 27 - Absolute Maximum Ratings

HD151TS207SSRev.1.00, Apr.25.2003, page 33 of 38DC Electrical Characteristics / USB & VCH 48MHz Clock(CK409T Type3A Buffer)Ta = 0°C to 70°C, VDD

Strany 28 - Ta = 0°C to 70°C, VDD = 3.3 V

HD151TS207SSRev.1.00, Apr.25.2003, page 34 of 38DC Electrical Characteristics / DOT Clock (CK409T Type3B Buffer)Ta = 0°C to 70°C, VDD = 3.3 VItem Sy

Strany 29

HD151TS207SSRev.1.00, Apr.25.2003, page 35 of 38DC Electrical Characteristics / REF Clock (CK409T Type5 Buffer)Ta = 0°C to 70°C, VDD = 3.3 VItem Sym

Strany 30

HD151TS207SSRev.1.00, Apr.25.2003, page 36 of 38Clock Outtcycle nt = (tcycle n) - (tcycle n+1)CCStcycle n+1Fig.1 Cycle to Cycle Jitter (3.3V

Strany 31 - = 30 pF

HD151TS207SSRev.1.00, Apr.25.2003, page 37 of 38Package DimensionsUnit : mm0.10(0.004)7.50128295618.400.25 0.6350.32.610.350.760.50˚– 8˚0.2

Strany 32

HD151TS207SSRev.1.00, Apr.25.2003, page 38 of 38Keep safety first in your circuit designs!1. Renesas Technology Corporation puts the maximum effort

Strany 33 - (CK409T Type3A Buffer)

HD151TS207SSRev.1.00, Apr.25.2003, page 4 of 38Pin DescriptionsPin name No. Type DescriptionVSS_A 54 Ground for PLLVSS_CPU 45 Ground for outputsVSS_

Strany 34 - = 10 pF

HD151TS207SSRev.1.00, Apr.25.2003, page 5 of 38Pin Descriptions (cont.)Pin name No. Type DescriptionPWRDWN#/SAFE_F#21 INPUTPULL–UP*PWRDWN# / SAFE_F#

Strany 35

HD151TS207SSRev.1.00, Apr.25.2003, page 6 of 38Block Diagram3V66[3:1]1/M2SSC21/N21/M1SSC11/N11/M01/N0OSCCK2CK1CK0XTAL14.318 MHzREF[1:0] (14.318MHz)C

Strany 36

HD151TS207SSRev.1.00, Apr.25.2003, page 7 of 38I2C Controlled Register Bit MapByte0 Control RegisterBit Description Contents Type Default Note7 Rese

Strany 37 - Package Dimensions

HD151TS207SSRev.1.00, Apr.25.2003, page 8 of 38I2C Controlled Register Bit Map (cont.)Table3 FS_A and FS_B pin Input levelLogic Level Min Voltage Ma

Strany 38

HD151TS207SSRev.1.00, Apr.25.2003, page 9 of 38I2C Controlled Register Bit Map (cont.)Table4 CPU Clock Power Management Truth TableSignal PinPWRDWN#

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