5.5. Limitations on SFR operation
Table 4 lists the limitations on a register operation. Also, the monitor program does not
operate properly when the register to which the change is disabled is changed.
Table 4 Limitations on SFR Operation
Register Default
Value
Limitation Change
Processor Mode Register 0 Reset to 00h Single-chip mode only
∗
Processor Mode Register 1 Reset to 00h ----------------------
√
System Clock Control Register 0 Reset to 08h Set the CM05 bit to “0”.
∗
System Clock Control Register 1 Reset to 28h Set the CM13, CM15 bit to “1”.
∗
High-Speed On-Chip Oscillator Control Register
0
Reset to 03h ----------------------
√
High-Speed On-Chip Oscillator Control Register
1
---------------------- ----------------------
√
High-Speed On-Chip Oscillator Control
Register 2
Reset to 03h ----------------------
√
Oscillation Stop Detection Register Reset to 00h ---------------------- N/A
Protect Register ---------------------- ----------------------
√
Flag Register ---------------------- Writing to the D flag is ignored
Do not set to “1”.
∗
ISP
(Interrupt Stack Pointer)
Reset to 057Fh Set the value of 06FFh or below.
06FFh to 07FFh are used for the monitor
program..
∗
UART 1 Transmit/Receive Mode Register 15h
UART 1 Bit Rate Register ----------------------
UART 1 Transmit/Receive Control Register 0 00h
UART 1 Transmit/Receive Control Register 1 07h
UART 1 Function Selection Register ----------------------
Port Mode Register 10h
Do no change. N/A
UART 1 Transmit Buffer Register ---------------------- Do not write data to this register. N/A
UART 1 Receive Buffer Register ---------------------- Do not write data to this register. N/A
√ : Possible to change N/A : Disable to change ∗ : Possible to change (Limitations in part)
5.6. Limitations on stop mode or wait mode
When using stop mode or wait mode on a user program, start the R8C UART debugger in
free-run mode, and close a RAM window, C watch window and an ASM window in advance.
Also, do not operate the R8C UART debugger until the program stops at the break point by
setting the break point after exiting stop mode or wait mode.
5.7. Watchdog timer
The watchdog timer is refreshed while the monitor program operates. If the monitor program
operates by referring or changing memory contents during the user program execution
which uses the watchdog timer, note that the watchdog timer will be refreshed.
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