Renesas SuperH SH7710 E10A Uživatelský manuál stáhnout pdf (Strana 17)

Peripherals

• An interrupt request can be sent to the CPU on

completion of the specified number of transfers

• Various DMAC transfer requests are provided:

– External request

– On-chip peripheral modules (Transfer requests from the

SCI, SCF, and TMU can be accepted on all channels.)

– Auto-request (A transfer request is generated

automatically within the DMAC)

• Channel functions: different transfer modes

can be set for each channel

■ Data Transfer Controller (DTC)

• Transfer possible over any number of channels

• 3 transfer modes: normal, repeat, and block transfer

• One activation source can trigger a number of data

transfers (chain transfer)

• Direct specification of 32-bit address space

• Activation by software allowed

• Transfer can be set in byte, word, or longword units

■ Host Interface (HIF)

• Connectable to the main CPU with parallel bus

• HIF boot function eliminates the need for boot ROM

■ Motor Management Timer (MMT)

• Triangular-wave comparison-type 6-phase PWM

waveform output with non-overlap dead times

• Non-overlap times generated by timer’s dead time

counters decrease torque pulsations/ harmonics for

improved voltage utilization

• Toggle output synchronized with PWM period

• PWM output halted by external signal

• PWM duty programmable between 0 and 100%

• Output-off functions

• Adjustable carrier frequency for low switching losses

and less audible noise

■ Multi-function Timer Unit (MTU)

• Up to 12-phase PWM output with synchronous

operation

• 2-phase encoder pulse up/down count

• Counter cascade mode to 32-bit counter

• High sink current (15mA) for 6 pins; can directly

drive opto-isolators

• A/D converter trigger signal can be generated

• Dead time can be generated automatically

■ Analog Interfaces

• 4- to 32-channel 10-bit successive-approximation

A/D converter

– Precise current detection for current control

– Three sample-and-holds with maximum conversion time

of 5.4 microseconds

• 2 channel 8-bit D/A converter

SuperH Main On-chip Peripherals

DTC

service

request

Interrupt

controller

On-chip 1KB RAM

Channel n

Interrupt

request

n + 1

n + 2

Source

Memory data

Destination

DMA Register

Source

Serial I/O

Destination

Memory

Data Transfer Controller Block Diagram

Main

CPU

LAN port

LAN

16 bits

Main CPU bus

SH7618

SH local bus

Flash

memory

Connectable with general bus

HIF

RAM

SH-2

Cache

E-

DMAC

Ether-C

PHY

SDRAM

Flash

memory

Optional

Boot ROM

SH7619

Host Interface Block Diagram

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 ... 41 42

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