Renesas MN4 Specifikace stáhnout pdf (Strana 21)

V850E2/MN4 UARTJ Control

R01AN0926EJ0100 Rev.1.00 Page 21 of 30

Feb 07, 2012

4.2.6 FIFO Control Register 1 (URTJnFCTL1)

The URTJnFCTL1 register controls the Rx timeout detection.

A timeout error occurs, when the receive FIFO is not empty and when no receive data is stored in the receive FIFO or

no data is read from the receive FIFO for a certain period of time.

Figure 4.13 URTJnFCTL1 Register Format

Setting example:

URTJnFCTL1 = 0x3F; /* Detect timeout */

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Renesas MN4 Specifikace Strana 21