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Renesas PCA4738L-64A Technické informace Strana 20

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
17
I/O PORTS
Direction Registers
The 3825 group has 43 programmable I/O pins arranged in seven
I/O ports (ports P1
6, P17, P2, P4–P6, P71–P77, P80 and P81). The
I/O ports have direction registers which determine the input/output
direction of each individual pin. (Ports P1
6 and P17 are shared
with bits 6 and 7 of the port P1 output control register). Each bit in
a direction register corresponds to one pin, and each pin can be
set to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are
floating. If a pin set to input is written to, only the port output latch
is written to and the pin remains floating.
Port P1 Output Control Register
Bit 0 of the port P1 output control register (address 000316) en-
ables control of the output of ports P1
0 to P15.
When the bit is set to “1”, the port output function is valid.
In this case, setting of the PULL register A to ports P1
0 to P15 is
invalid.
When resetting, bit 0 of the port P1 output control register is set to
“0” (the port output function is invalid.)
Pull-up/Pull-down Control
By setting the PULL register A (address 001616) or the PULL reg-
ister B (address 0017
16), ports P0 to P8 except P70 can control ei-
ther pull-down or pull-up (pins that are shared with the segment
output pins for LCD are pull-down; all other pins are pull-up) with
a program.
However, the contents of PULL register A and PULL register B do
not affect ports programmed as the output ports. (except for ports
P0 and P3).
Ports P0 and P3 share the port output control function with bit 0 of
the PULL register A. When set to “1”, the port output function is in-
valid (Pull-down is valid).
When set to “0”, the port output function is valid (Pull-down is in-
valid).
The PULL register A setting is invalid for pins set to segment out-
put with the segment output enable register.
Fig. 13 Structure of PULL register A and PULL register B
P
0
,
P
1
0–
P
1
5,
P
3
p
u
l
l
-
d
o
w
n
(
s
h
a
r
e
d
w
i
t
h
P
0
a
n
d
P
3
o
u
t
p
u
t
c
o
n
t
r
o
l
:
r
e
f
e
r
t
o
t
h
e
t
e
x
t
)
P
1
6–
P
17
p
u
l
l
-
u
p
P
2
0–
P
27
p
u
l
l
-
u
p
P
8
0,
P
81
p
u
l
l
-
u
p
P
4
0–
P
43
p
u
l
l
-
u
p
P
4
4–
P
47
p
u
l
l
-
u
p
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
0
”
w
h
e
n
r
e
a
d
)
PULL
reg
i
ster
A
(PULLA : address 001616)
b
7
b
0
P
5
0–
P
5
3
p
u
l
l
-
u
p
P
54–
P
57
p
u
l
l
-
u
p
P
6
0–
P
63
p
u
l
l
-
u
p
P
6
4–
P
67
p
u
l
l
-
u
p
P
7
1–
P
73
p
u
l
l
-
u
p
P
7
4–
P
77
p
u
l
l
-
u
p
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
0
”
w
h
e
n
r
e
a
d
)
0
:
D
i
s
a
b
l
e
1
:
E
n
a
b
l
e
P
U
L
L
r
e
g
i
s
t
e
r
B
(
P
U
L
L
B
:
a
d
d
r
e
s
s
0
0
1
71
6)
b
7
b
0
N
ote:
Th
e contents o
f
PULL
reg
i
ster
A
an
d
PULL
reg
i
ster
B
do not affect ports programmed as the output port.
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