Renesas PROM Programming Adapter PCA7435FPG02 Uživatelský manuál stáhnout pdf (Strana 42)

7540 Group

Rev.4.00 Jun 21, 2004 page 42 of 82

REJ03B0011-0400Z

Reset Circuit

The microcomputer is put into a reset status by holding the RE-

SET pin at the “L” level for 2 µs or more when the power source

voltage is 2.2 to 5.5 V and XIN is in stable oscillation.

After that, this reset status is released by returning the RESET pin

to the “H” level. The program starts from the address having the

contents of address FFFD16 as high-order address and the con-

tents of address FFFC16 as low-order address.

In the case of f(φ) ≤ 6 MHz, the reset input voltage must be 0.9 V

or less when the power source voltage passes 4.5 V.

In the case of f(φ) ≤ 4 MHz, the reset input voltage must be 0.8 V

or less when the power source voltage passes 4.0 V.

In the case of f(φ) ≤ 2 MHz, the reset input voltage must be 0.48 V

or less when the power source voltage passes 2.4 V.

In the case of f(φ) ≤ 1 MHz, the reset input voltage must be 0.44 V

or less when the power source voltage passes 2.2 V.

Fig. 43 Example of reset circuit

Fig. 44 Timing diagram at reset

(Note)

0.2 V

0 V

Poweron

VCCRESET

VCC

RESET

Power source

voltage

detection circuit

Power source

voltage

Reset input

voltage

Note : Reset release voltage Vcc = 2.2 V

Data

Address

8-13 clock cycles

Reset address from the

vector table

1 : An on-chip oscillator applies about RING•2 MHz, φ•250 kHz frequency clock

at average of Vcc = 5 V.

2 : The mark “?” means that the address is changeable depending on the previous state.

3 : These are all internal signals except RESET.

Notes

FFFC FFFD

,AD

???

Clock from on-chip

oscillator RING

RESET

OUT

SYNC

1 2 ... 37 38 39 40 41 42 43 44 45 46 47 ... 87 88

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