Renesas M65881AFP Uživatelský manuál stáhnout pdf (Strana 12)

Rev.1.00 2003.05.08

page 12 of 23

M65881AFP

13. Power sequences

System power-on sequencing * Refer to following figure.

Power(Vddxxx, HPVddxxx,

XVdd, XOVdd, DVdd, BFVdd)

Master clock

(XfsoIN,XfsiIN)

INIT

SCDT

SCSHIFT

SCLATCH

Over 5msec(*1)

Over 0sec(*2)

Over 2/fso(*3)

Power ON

Power OFF

*1 After a power supply and Master clock become to stable, INIT pin must be "L" over 5msec.

*2 Data transfer is possible right after INIT release.

*3 Until SCLATCH is operated, a period over 2/fso ( fso=48kHz, over 42µsec ) is necessary after INIT release.

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 22 23

Žádné komentáře

Renesas M65881AFP Uživatelský manuál Strana 12