Renesas H8/325 Series Manuál

To all our customersRegarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp.The s

Rev. 3.0, 09/98, page vii of viiiSection 15 Power-Down State...

Rev. 3.0, 09/98, page 90 of 361Input Pull-Up Transistors: Port 2 has built-in programmable input pull-up transistors that areavailable in modes 2 and

Rev. 3.0, 09/98, page 91 of 361Figure 6.2 shows a schematic diagram of port 2.P2nHardware standbyMode 3Mode 1 or 2RP2ResetResetMode 1ResetWP2WP2DWP2PR

Rev. 3.0, 09/98, page 92 of 3616.4 Port 3Port 3 is an 8-bit input/output port that also provides the external data bus. The function of port 3depends

Rev. 3.0, 09/98, page 93 of 361P3DR is an 8-bit register containing the data for pins P37 to P30. When the CPU reads P3DR, foroutput pins it reads th

Rev. 3.0, 09/98, page 94 of 361Table 6.10 indicates the states of the input pull-up transistors in each operating mode.Table 6.10 States of Input Pull

Rev. 3.0, 09/98, page 95 of 361Figure 6.3 shows a schematic diagram of port 3.P3nResetResetResetWP3WP3DWP3PRRRQQQDDDP3n DRP3n DDRP3n PCRCCCRP3External

Rev. 3.0, 09/98, page 96 of 3616.5 Port 4Port 4 is an 8-bit input/output port that also provides the input and output pins for the 8-bit timersand the

Rev. 3.0, 09/98, page 97 of 361Port 4 Data Register (P4DR)H'FFB7Bit:76543210P47P46P45P44P43P42P41P40Initial value:00000000Read/Write: R/W R/W R/

Rev. 3.0, 09/98, page 98 of 361Figures 6.4 (a) and 6.4 (b) show schematic diagrams of port 4.P4nRP4ResetInternal data busResetWP4WP4DRRQQDDP4n DRP4n D

Rev. 3.0, 09/98, page 99 of 361RP4ResetResetWP4WP4DRRQQDDP4n DRP4n DDRCCWP4D:WP4:RP4:n = 1, 4, 6, 7Write Port 4 DDRWrite Port 4Read Port 48-bit timer

Rev. 3.0, 09/98, page viii of viiiAppendix C Pin States...

Rev. 3.0, 09/98, page 100 of 3616.6 Port 5Port 5 is a 3-bit input/output port that also provides the input and output pins for serial communi-cation i

Rev. 3.0, 09/98, page 101 of 361Port 5 Data Register (P5DR)H'FFBABit:76543210P52P51P50Initial value:11111000Read/Write: R/W R/W R/WP5D

Rev. 3.0, 09/98, page 102 of 361Figures 6.5 (a) to 6.5 (c) show schematic diagrams of port 5.RP5ResetResetInternal data busWP5WP5DRRQQDDP50 DRP50 DDRC

Rev. 3.0, 09/98, page 103 of 361P51 RP5ResetResetWP5WP5DRRQQDDP51 DRP51DDRCCWP5D:WP5:RP5:Write Port 5 DDRWrite Port 5 Read Port 5SCI moduleReceive ena

Rev. 3.0, 09/98, page 104 of 361RP5ResetResetWP5WP5DRRQQDDP52 DRP52 DDRCCWP5D:WP5:RP5:Write Port 5 DDRWrite Port 5Read Port 5SCI moduleInternal data b

Rev. 3.0, 09/98, page 105 of 3616.7 Port 6Port 6 is an 8-bit input/output port that also provides the input and output pins for the free-runningtimer

Rev. 3.0, 09/98, page 106 of 361Port 6 Data Register (P6DR)H'FFBBBit:76543210P67P66P65P64P63P62P61P60Initial value:00000000Read/Write: R/W R/W R

Rev. 3.0, 09/98, page 107 of 361Figures 6.6 (a) to 6.6 (d) shows schematic diagrams of port 6.P6nRP6ResetInternal data busResetWP6WP6DRRQQDDP6n DRP6n

Rev. 3.0, 09/98, page 108 of 361RP6ResetResetWP6WP6DRRQQDDP61 DRP61 DDRCCWP6D:WP6:RP6:Write Port 6 DDRWrite Port 6Read Port 6Free-runningtimer moduleO

Rev. 3.0, 09/98, page 109 of 361RP6ResetResetInternal data busWP6WP6DRRQQDDP66 DRP66 DDRCCWP6D:WP6:RP6:Write Port 6 DDRWrite Port 6Read Port 6Free-run

Rev. 3.0, 09/98, page 1 of 361Section 1 Overview1.1 OverviewThe H8/338 Series of single-chip microcomputers features an H8/300 CPU core and acomplem

Rev. 3.0, 09/98, page 110 of 361P67RP6ResetResetInternal data busWP6WP6DRRQQDDP67 DRP67 DDRCCWP6D:WP6:RP6:Write Port 6 DDR Write Port 6Read Port 6IRQ

Rev. 3.0, 09/98, page 111 of 3616.8 Port 7Port 7 is an 8-bit input port that also provides the analog input pins for the A/D converter module,and anal

Rev. 3.0, 09/98, page 112 of 361P7nRP7: Read port 7n = 0 to 5A/D converter moduleInternal data busAnalog inputRP7Figure 6.7 (a) Port 7 Schematic Di

Rev. 3.0, 09/98, page 113 of 3616.9 Port 8Port 8 is a 7-bit input/output port that also provides pins for interrupt input and serialcommunication. Ta

Rev. 3.0, 09/98, page 114 of 361Port 8 Data Register (P8DR)H'FFBFBit:76543210P86P85P84P83P82P81P80Initial value:10000000Read/Write:  R/W R/W R

Rev. 3.0, 09/98, page 115 of 361Figures 6.8 (a) to 6.8 (d) show schematic diagrams of port 8.P8nRP8Reset Internal data busResetWP8WP8DRRQQDDP8n DRP8n

Rev. 3.0, 09/98, page 116 of 361RP8ResetInternal data busResetWP8WP8DRRQQDDP84 DRP84 DDRCCWP8D:WP8:RP8:Write Port 8 DDRWrite Port 8Read Port 8Transmit

Rev. 3.0, 09/98, page 117 of 361RP8ResetWP8RQDP85 DRCWP8D:WP8:RP8:Write Port 8 DDRWrite Port 8Read Port 8SCI moduleReceive enableInternal data busP85I

Rev. 3.0, 09/98, page 118 of 361RP8ResetResetWP8WP8DRRQQDDP86 DRP86 DDRCCWP8D:WP8:RP8:Write Port 8 DDRWrite Port 8Read Port 8SCI moduleClock input ena

Rev. 3.0, 09/98, page 119 of 3616.10 Port 9Port 9 is an 8-bit input/output port that also provides pins for interrupt input (IRQ0 to IRQ2), A/Dtrigger

Rev. 3.0, 09/98, page 2 of 361Table 1.1 FeaturesItem SpecificationCPU Two-way general register configuration• Eight 16-bit registers, or• Sixteen 8-bi

Rev. 3.0, 09/98, page 120 of 361Port 9 Data Direction Register (P9DDR)H'FFC0Bit 76543210P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDRM

Rev. 3.0, 09/98, page 121 of 361Pin P97: In modes 1 and 2, this pin is used for input of the WAIT bus control signal. It isunaffected by the values

Rev. 3.0, 09/98, page 122 of 361Figures 6.9 (a) to 6.9 (e) show schematic diagrams of port 9.P90RP9ResetInternal data busResetWP9WP9DRRQQDDP90 DRP90 D

Rev. 3.0, 09/98, page 123 of 361P9nRP9ResetResetWP9WP9DRRQQDDP9n DRP9n DDRCCWP9D:WP9:RP9:n = 1, 2Write Port 9 DDR Write Port 9Read Port 9IRQ0 inputIRQ

Rev. 3.0, 09/98, page 124 of 361RP9ResetResetWP9WP9DRRQQDDP9n DRP9n DDRCCWP9D:WP9:RP9:n = 3, 4, 5Write Port 9 DDRWrite Port 9Read Port 9RD outputWR ou

Rev. 3.0, 09/98, page 125 of 361P96RP9ResetInternal data busMode 1, 2WP9DRSQDP96DDRCWP9D:WP9:RP9:Note: * Set-priorityWrite Port 9 DDRWrite Port 9 Rea

Rev. 3.0, 09/98, page 126 of 361P97 RP9ResetResetInternal data busWP9WP9DRRQQDDP97 DRP97DDRCCWP9D:WP9:RP9:Write Port 9 DDRWrite Port 9 Read Port 9Mode

Rev. 3.0, 09/98, page 127 of 361Section 7 16-Bit Free-Running Timer7.1 OverviewThe H8/338 Series has an on-chip 16-bit free-running timer (FRT) modu

Rev. 3.0, 09/98, page 128 of 361Externalclock sourceFTOAFTOBFTIAFTIBFTICFTIDInternalclock sourcesØ/2Ø/8Ø/32FTCIClockOverflowClearCompare-match BContro

Rev. 3.0, 09/98, page 129 of 3617.1.3 Input and Output PinsTable 7.1 lists the input and output pins of the free-running timer module.Table 7.1 Input

Rev. 3.0, 09/98, page 3 of 361Table 1.1 Features (cont)Item SpecificationA/D converter• 8-bit resolution• Eight channels: single or scan mode (selecta

Rev. 3.0, 09/98, page 130 of 361Table 7.2 Register Configuration (cont)Name Abbreviation R/W Initial Value AddressInput capture register B (High) ICRB

Rev. 3.0, 09/98, page 131 of 3617.2.2 Output Compare Registers A and B (OCRA and OCRB)H'FF94Bit:1514131211109876543210Initial value:111111111111

Rev. 3.0, 09/98, page 132 of 361Input capture can be buffered by using the input capture registers in pairs. When the BUFEA bitin the timer control r

Rev. 3.0, 09/98, page 133 of 361Table 7.3 Buffered Input Capture Edge Selection (Example)IEDGA IEDGC Input Capture Edge0 0 Captured on falling edge of

Rev. 3.0, 09/98, page 134 of 3617.2.4 Timer Interrupt Enable Register (TIER)-H'FF90Bit:76543210ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE Initial

Rev. 3.0, 09/98, page 135 of 361Bit 4Input Capture Interrupt D Enable (ICIDE): This bit selects whether to request inputcapture interrupt D (ICID) w

Rev. 3.0, 09/98, page 136 of 3617.2.5 Timer Control/Status Register (TCSR)H'FF91Bit:76543210ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRAInitial value

Rev. 3.0, 09/98, page 137 of 361Bit 6Input Capture Flag B (ICFB): This status bit is set to “1” to flag an input capture Bevent. If BUFEB = “0,” IC

Rev. 3.0, 09/98, page 138 of 361Bit 3Output Compare Flag A (OCFA): This status flag is set to “1” when the FRC valuematches the OCRA value. This fl

Rev. 3.0, 09/98, page 139 of 3617.2.6 Timer Control Register (TCR)-H'FF96Bit:76543210IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0Initial value:0

Rev. 3.0, 09/98, page 4 of 3611.2 Block DiagramFigure 1.1 shows a block diagram of the H8/338 Series.Port 4 Port 7 Port 5Port 8 Port 3 Port 9Port 6CPU

Rev. 3.0, 09/98, page 140 of 361Bit 4Input Edge Select D (IEDGD): This bit causes input capture D events to be recognizedon the selected edge of the

Rev. 3.0, 09/98, page 141 of 3617.2.7 Timer Output Compare Control Register (TOCR)H'FF97Bit:76543210OCRS OEA OEB OLVLA OLVLBInitial value:111

Rev. 3.0, 09/98, page 142 of 361Bit 1Output Level A (OLVLA): This bit selects the logic level to be output at the FTOA pinwhen the FRC and OCRA valu

Rev. 3.0, 09/98, page 143 of 3617.3 CPU InterfaceThe free-running counter (FRC), output compare registers (OCRA and OCRB), and input captureregisters

Rev. 3.0, 09/98, page 144 of 361(1) Upper byte writeBus interfaceCPU writes data H'AATEMP[H'AA]FRC H[ ]FRC L[ ]Module data bus(2) Lowe

Rev. 3.0, 09/98, page 145 of 361(1) Upper byte readBus interfaceBus interfaceCPU reads data H'AATEMP[H'55]FRC H[H'AA]FRC L[H'55]M

Rev. 3.0, 09/98, page 146 of 3617.4 Operation7.4.1 FRC Incrementation TimingThe FRC increments on a pulse generated once for each period of the select

Rev. 3.0, 09/98, page 147 of 361N N + 1FTCIFRC clock pulseFRCØFigure 7.5 Increment Timing for External Clock SourceNNNNN + 1N + 1FRCOCRAØInternal co

Rev. 3.0, 09/98, page 148 of 3617.4.2 Output Compare Timing(1) Setting of Output Compare Flags A and B (OCFA and OCFB): The output compare flagsare

Rev. 3.0, 09/98, page 149 of 361(3) FRC Clear Timing: If the CCLRA bit in the TCSR is set to “1,” the FRC is cleared whencompare-match A occurs. Fi

Rev. 3.0, 09/98, page 5 of 3611.3 Pin Assignments and Functions1.3.1 Pin ArrangementFigure 1.2 shows the pin arrangement of the CG-84 package. Figure

Rev. 3.0, 09/98, page 150 of 361If the upper byte of ICRA/B/C/D is being read when the corresponding input capture signalarrives, the internal input c

Rev. 3.0, 09/98, page 151 of 361Figure 7.13 shows how input capture operates when ICRA and ICRC are used in buffer mode andIEDGA and IEDGC are set to

Rev. 3.0, 09/98, page 152 of 3617.4.4 Setting of FRC Overflow Flag (OVF)The FRC overflow flag (OVF) is set to “1” when the FRC overflows (changes from

Rev. 3.0, 09/98, page 153 of 3617.6 Sample ApplicationIn the example below, the free-running timer is used to generate two square-wave outputs with a5

Rev. 3.0, 09/98, page 154 of 3617.7 Application NotesApplication programmers should note that the following types of contention can occur in the free-

Rev. 3.0, 09/98, page 155 of 361Figure 7.18 shows this type of contention.ØInternal address busInternal write signalFRCOCRA or OCRBCompare-match A or

Rev. 3.0, 09/98, page 156 of 361(4) Incrementation Caused by Changing of Internal Clock Source: When an internal clocksource is changed, the changeo

Rev. 3.0, 09/98, page 157 of 361Table 7.5 Effect of Changing Internal Clock Sources (cont)No. Description Timing chart3 High → Low:CKS1 and CKS0 arere

Rev. 3.0, 09/98, page 159 of 361Section 8 8-Bit Timers8.1 OverviewThe H8/338 Series includes an 8-bit timer module with two channels (TMR0 and TMR1)

Rev. 3.0, 09/98, page 160 of 3618.1.2 Block DiagramFigure 8.1 shows a block diagram of one channel in the 8-bit timer module. The other channel iside

Rev. 3.0, 09/98, page 6 of 3611213141516171819202122232425262728293031327473727170696867666564636261605958575655541133RESXTALEXTALMD1MD0NMISTBYVCCP52/

Rev. 3.0, 09/98, page 161 of 3618.1.3 Input and Output PinsTable 8.1 lists the input and output pins of the 8-bit timer.Table 8.1 Input and Output Pin

Rev. 3.0, 09/98, page 162 of 3618.2 Register Descriptions8.2.1 Timer Counter (TCNT)H'FFCC (TMR0), H'FFD4 (TMR1)Bit:76543210Initial value:00

Rev. 3.0, 09/98, page 163 of 361Compare-match is not detected during the T3 state of a write cycle to TCORA or TCORB. Seeitem (3) in section 8.6, “Ap

Rev. 3.0, 09/98, page 164 of 361Bit 5Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a timeroverflow interrupt (OVI) whe

Rev. 3.0, 09/98, page 165 of 361Bits 2, 1, and 0Clock Select (CKS2, CKS1, and CKS0): These bits and bits ICKS1 andICKS0 in the serial/timer control

Rev. 3.0, 09/98, page 166 of 3618.2.4 Timer Control/Status Register (TCSR)H'FFC9 (TMR0), H'FFD1 (TMR1)Bit:76543210CMFB CMFA OVF  OS3 OS2 O

Rev. 3.0, 09/98, page 167 of 361Bit 5Timer Overflow Flag (OVF): This status flag is set to “1” when the timer countoverflows (changes from H'FF

Rev. 3.0, 09/98, page 168 of 3618.2.5 Serial/Timer Control Register (STCR)H'FFC3Bit:76543210MPE ICKS1 ICKS0Initial value:11111000Read/Write

Rev. 3.0, 09/98, page 169 of 3618.3 Operation8.3.1 TCNT Incrementation TimingThe timer counter increments on a pulse generated once for each period of

Rev. 3.0, 09/98, page 170 of 361NN - 1N + 1External clock sourceTCNT clockpulseØTCNTFigure 8.3 Count Timing for External Clock Input8.3.2 Compare Ma

Rev. 3.0, 09/98, page 7 of 3611234567891011121314151617181920605958575655545352515049484746454443424180 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 6

Rev. 3.0, 09/98, page 171 of 361(2) Output Timing: When a compare-match event occurs, the timer output (TMO0 or TMO1)changes as specified by the out

Rev. 3.0, 09/98, page 172 of 3618.3.3 External Reset of TCNTWhen the CCLR1 and CCLR0 bits in the TCR are both set to “1,” the timer counter is cleared

Rev. 3.0, 09/98, page 173 of 3618.4 InterruptsEach channel in the 8-bit timer can generate three types of interrupts: compare-match A and B(CMIA and

Rev. 3.0, 09/98, page 174 of 3618.6 Application NotesApplication programmers should note that the following types of contention can occur in the 8-bit

Rev. 3.0, 09/98, page 175 of 361(2) Contention between TCNT Write and Increment: If a timer counter increment pulse isgenerated during the T3 state

Rev. 3.0, 09/98, page 176 of 361(3) Contention between TCOR Write and Compare-Match: If a compare-match occursduring the T3 state of a write cycle t

Rev. 3.0, 09/98, page 177 of 361(5) Incrementation Caused by Changing of Internal Clock Source: When an internal clocksource is changed, the changeo

Rev. 3.0, 09/98, page 178 of 361Table 8.5 Effect of Changing Internal Clock Sources (cont)No. Description Timing chart3 High → Low*1:Clock select bits

Rev. 3.0, 09/98, page 179 of 361Section 9 PWM Timers9.1 OverviewThe H8/338 Series has an on-chip pulse-width modulation (PWM) timer module with twoi

Rev. 3.0, 09/98, page 180 of 3619.1.2 Block DiagramFigure 9.1 shows a block diagram of one PWM timer channel.PulseDTROutputcontrolComparatorTCNTTCRInt

Rev. 3.0, 09/98, page 8 of 3611.3.2 Pin Functions(1) Pin Assignments in Each Operating Mode: Table 1.2 lists the assignments of the pins ofthe FP-80

Rev. 3.0, 09/98, page 181 of 3619.1.3 Input and Output PinsTable 9.1 lists the output pins of the PWM timer module. There are no input pins.Table 9.1

Rev. 3.0, 09/98, page 182 of 3619.2.2 Duty Register (DTR)H'FFA1 (PWM0), H'FFA5 (PWM1)Bit:76543210Initial value:11111111Read/Write: R/W R/W

Rev. 3.0, 09/98, page 183 of 361Bit 7Output Enable (OE): This bit enables the timer counter and the PWM output.Bit 7OE Description0 PWM output is di

Rev. 3.0, 09/98, page 184 of 361Table 9.3 PWM Timer Parameters for 10MHz System ClockInternal Clock Frequency Resolution PWM Period PWM Frequencyφ/2 2

Rev. 3.0, 09/98, page 185 of 3619.3.2 PWM OperationFigure 9.3 is a timing chart of the PWM operation.N(a) H' 00 (b) H' 01 H' 02 H'

Rev. 3.0, 09/98, page 186 of 361iii) If the DTR value is changed (by writing the data “M” in figure 9.3), the new valuebecomes valid after the timer c

Rev. 3.0, 09/98, page 187 of 361Section 10 Serial Communication Interface10.1 OverviewThe H8/338 Series includes two serial communication interface

Rev. 3.0, 09/98, page 188 of 361TDR-empty, TSR-empty, receive-end, and receive-error interrupts are requestedindependently.10.1.2 Block DiagramFigure

Rev. 3.0, 09/98, page 189 of 361Table 10.1 SCI Input/Output PinsChannel Name Abbr. I/O Function0 Serial clock SCK0Input/output Serial clock input and

Rev. 3.0, 09/98, page 190 of 36110.2 Register Descriptions10.2.1 Receive Shift Register (RSR)Bit:76543210Read/Write: The RSR is a shift regist

Hitachi Single-Chip MicrocomputerH8/338 SeriesH8/338HD6473388, HD6433388, HD6413388H8/337HD6473378, HD6433378, HD6413378H8/336HD6433368Hardware Manual

Rev. 3.0, 09/98, page 9 of 361Table 1.2 Pin Assignments in Each Operating Mode (cont)Pin No. Expanded Modes Single-Chip ModeCP-84CG-84 FP-80A Mode 1 M

Rev. 3.0, 09/98, page 191 of 36110.2.4 Transmit Data Register (TDR)H'FFDB, H'FF8BBit:76543210Initial value:11111111Read/Write: R/W R/W R/W

Rev. 3.0, 09/98, page 192 of 361Bit 6Character Length (CHR): This bit selects the character length in asynchronous mode. Itis ignored in synchronou

Rev. 3.0, 09/98, page 193 of 361Bit 3Stop Bit Length (STOP): This bit selects the number of stop bits. It is ignored in thesynchronous mode.Bit 3ST

Rev. 3.0, 09/98, page 194 of 36110.2.6 Serial Control Register (SCR)H'FFDA, H'FF8ABit:76543210TIE RIE TE RE MPIE TEIE CKE1 CKE0Initial valu

Rev. 3.0, 09/98, page 195 of 361Bit 4Receive Enable (RE): This bit enables or disables the receive function. When the receivefunction is enabled, t

Rev. 3.0, 09/98, page 196 of 361Bit 2Transmit-End Interrupt Enable (TEIE): This bit enables or disables the TSR-emptyinterrupt (TEI) requested when

Rev. 3.0, 09/98, page 197 of 36110.2.7 Serial Status Register (SSR)H'FFDC, H'FF8CBit:76543210TDRE RDRF ORER FER PER TEND MPB MPBTInitial va

Rev. 3.0, 09/98, page 198 of 361Bit 4Framing Error (FER): This bit indicates a framing error during data reception inasynchronous mode. It has no m

Rev. 3.0, 09/98, page 199 of 361Bit 1Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in data received ina multiprocessor format

Rev. 3.0, 09/98, page 200 of 36110.2.8 Bit Rate Register (BRR)H'FFD9, H'FF89Bit:76543210Initial value:11111111Read/Write: R/W R/W R/W R/W R

Rev. 3.0, 09/98, page 10 of 361Table 1.2 Pin Assignments in Each Operating Mode (cont)Pin No. Expanded Modes Single-Chip ModeCP-84CG-84 FP-80A Mode 1

Rev. 3.0, 09/98, page 201 of 361Table 10.3 Examples of BRR Settings in Asynchronous Mode (2)XTAL Frequency (MHz)4.9152 6 7.3728 8BitRate n NError(%) n

Rev. 3.0, 09/98, page 202 of 361Table 10.3 Examples of BRR Settings in Asynchronous Mode (4)XTAL Frequency (MHz)14.7456 16 19.6608 20BitRate n NError(

Rev. 3.0, 09/98, page 203 of 361Table 10.4 Examples of BRR Settings in Synchronous ModeXTAL Frequency (MHz)2 4 8 10 16 20BitRatenNnNnNnNnNnN100 

Rev. 3.0, 09/98, page 204 of 36110.2.9 Serial/Timer Control Register (STCR)H'FFC3Bit:76543210MPE ICKS1 ICKS0Initial value:11111000Read/Writ

Rev. 3.0, 09/98, page 205 of 36110.3 Operation10.3.1 OverviewThe SCI supports serial data transfer in two modes. In asynchronous mode each character

Rev. 3.0, 09/98, page 206 of 361Table 10.5 Communication Formats Used by SCISMR settings Communication FormatBit 7C/ABit 6CHRBit 2MPBit 5PEBit 3STOP M

Rev. 3.0, 09/98, page 207 of 36110.3.2 Asynchronous ModeIn asynchronous mode, each transmitted or received character is individually synchronized byfr

Rev. 3.0, 09/98, page 208 of 361Table 10.7 Data Formats in Asynchronous ModeCHR000011110011PE00110011————MP000000001111STOP010101010101SMR Bits1234567

Rev. 3.0, 09/98, page 209 of 361(3) Transmitting and Receiving Data• SCI Initialization: Before transmitting or receiving, software must clear the T

Rev. 3.0, 09/98, page 210 of 361• Transmitting Serial Data: Follow the procedure below for transmitting serial data.Start transmittingRead TDRE bit i

Rev. 3.0, 09/98, page 11 of 361(2) Pin Functions: Table 1.3 gives a concise description of the function of each pin.Table 1.3 Pin FunctionsPin No.Ty

Rev. 3.0, 09/98, page 211 of 361In transmitting serial data, the SCI operates as follows.1. The SCI monitors the TDRE bit in SSR. When TDRE is cleare

Rev. 3.0, 09/98, page 212 of 361• Receiving Serial Data: Follow the procedure below for receiving serial data.Start receivingRead RDRF bit in SSRRDRF

Rev. 3.0, 09/98, page 213 of 361In receiving, the SCI operates as follows.1. The SCI monitors the receive data line and synchronizes internally when i

Rev. 3.0, 09/98, page 214 of 361"1"Start bit"0" D0 D1 D7 0/1Stop bit"1"DataParity bitStart bit"0" D0 D1 D7 0/1

Rev. 3.0, 09/98, page 215 of 361TransmittingprocessorReceivingprocessor AReceivingprocessor BReceivingprocessor CReceivingprocessor DSerial communicat

Rev. 3.0, 09/98, page 216 of 361Start receivingSet MPIE bit to "1" in SCRRead RDRF bit in SSRRDRF = "1"?Read receive data from RDR

Rev. 3.0, 09/98, page 217 of 361Figure 10.11 shows an example of SCI receive operation using a multiprocessor format."1"Start bit"0&quo

Rev. 3.0, 09/98, page 218 of 36110.3.3 Synchronous Mode(1) Overview: In clocked synchronous mode, the SCI transmits and receives data insynchronizat

Rev. 3.0, 09/98, page 219 of 361(2) Transmitting and Receiving Data• SCI Initialization: The SCI must be initialized in the same way as in asynchron

Rev. 3.0, 09/98, page 220 of 3612. After loading the data from TDR into TSR, the SCI sets the TDRE bit to “1” and startstransmitting. If the TIE bit

Rev. 3.0, 09/98, page 12 of 361Table 1.3 Pin Functions (cont)Pin No.Type SymbolCG-84CP-84 FP-80A I/O Name and FunctionBus control WAIT 25 13 I Wait:

Rev. 3.0, 09/98, page 221 of 361Start receivingRead RDRF bit in SSRRDRF = "1"?Read receive data from RDR, and clear RDRF bit to "0"

Rev. 3.0, 09/98, page 222 of 361After receiving the data, the SCI checks that RDRF is “0” so that receive data can be loadedfrom RSR into RDR. If thi

Rev. 3.0, 09/98, page 223 of 361StartRead TDRE bit in SSRTDRE = "1"?Write transmit data in TDR and clear TDRE bit to "0" in SSRRDR

Rev. 3.0, 09/98, page 224 of 36110.4 InterruptsThe SCI can request four types of interrupts: ERI, RxI, TxI, and TEI. Table 10.9 indicates thesource a

Rev. 3.0, 09/98, page 225 of 361Table 10.10 SSR Bit States and Data Transfer when Multiple Receive Errors OccurSSR BitsReceive Error RDRF ORER FER PER

Rev. 3.0, 09/98, page 226 of 361Basic clock0123456789101112131415161234567891011121314151612345–7.5 pulsesStart bit+7.5 pulsesD0 D1Receive dataSync sa

Rev. 3.0, 09/98, page 227 of 361Section 11 A/D Converter11.1 OverviewThe H8/338 Series includes an analog-to-digital converter module with eight inp

Rev. 3.0, 09/98, page 228 of 36111.1.2 Block DiagramInternal data busADCRADCSRADDRAADDRBADDRCADDRDLegend:: A/D Control Register (8 bits): A/D Control/

Rev. 3.0, 09/98, page 229 of 36111.1.3 Input PinsTable 11.1 lists the input pins used by the A/D converter module.The eight analog input pins are divi

Rev. 3.0, 09/98, page 230 of 36111.2 Register Descriptions11.2.1 A/D Data Registers (ADDR)H'FFE0 to H'FFE6Bit:76543210ADDRn:Initial value:0

Rev. 3.0, 09/98, page 13 of 361Table 1.3 Pin Functions (cont)Pin No.Type SymbolCG-84CP-84 FP-80A I/O Name and FunctionFTOA,FTOB34392227O FRT Output co

Rev. 3.0, 09/98, page 231 of 361Bit 7A/D End Flag (ADF): This status flag indicates the end of one cycle of A/D conversion.Bit 7ADF Description0 To

Rev. 3.0, 09/98, page 232 of 361Bit 3Clock Select (CKS): This bit controls the A/D conversion time.The conversion time should be changed only when t

Rev. 3.0, 09/98, page 233 of 36111.2.3 A/D Control Register (ADCR)H'FFEABit:76543210TRGE CHSInitial value:01111110Read/Write: R/W R/

Rev. 3.0, 09/98, page 234 of 36111.3 OperationThe A/D converter performs 8 successive approximations to obtain a result ranging from H'00(corresp

Rev. 3.0, 09/98, page 235 of 361Value set in ADCSRADF ADIE ADST SCAN CKS CH2 CH1 CH001100001(2) The A/D converter converts the voltage level at the AN

Rev. 3.0, 09/98, page 236 of 361Interrupt (ADI)Set*Set*A/D conversion startsWaitingWaiting Waiting WaitingA/D conver-sion (1)A/D conver-sion (2)A/D co

Rev. 3.0, 09/98, page 237 of 36111.3.2 Scan Mode (SCAN = 1)The scan mode can be used to monitor analog inputs on one or more channels. When the ADSTb

Rev. 3.0, 09/98, page 238 of 361(4) After all selected channels (AN0 to AN2) have been converted, the AD converter sets the ADFbit to “1.” If the ADI

Rev. 3.0, 09/98, page 239 of 36111.3.3 Input Sampling Time and A/D Conversion TimeThe A/D converter includes a built-in sample-and-hold circuit. Samp

Rev. 3.0, 09/98, page 240 of 361ØInternaladdress busWrite signalInput samplingtimingADF(2)tDtSPL(1)(1)(2)tDtSPLtCONVLegend:: ADCSR write cycle: ADCSR

Rev. 3.0, 09/98, page 14 of 361Table 1.3 Pin Functions (cont)Pin No.Type SymbolCG-84CP-84 FP-80A I/O Name and FunctionGeneral-purposeI/OP17 to P1071 t

Rev. 3.0, 09/98, page 241 of 361Table 11.4 (b) A/D Conversion Time (Scan mode)CKS = “0” CKS = “1”Item Symbol Min Typ Max Min Typ MaxSynchronization

Rev. 3.0, 09/98, page 242 of 36111.4 InterruptsThe A/D conversion module generates an A/D-end interrupt request (ADI) at the end of A/Dconversion.The

Rev. 3.0, 09/98, page 243 of 361Section 12 D/A Converter12.1 OverviewThe H8/338 Series has an on-chip D/A converter module with two channels.12.1.1

Rev. 3.0, 09/98, page 244 of 36112.1.2 Block DiagramFigure 12.1 shows a block diagram of the D/A converter.Internal data busDACRDADR0DADR1: D/A contro

Rev. 3.0, 09/98, page 245 of 36112.1.3 Input and Output PinsTable 12.1 lists the input and output pins used by the D/A converter module.Table 12.1 Inp

Rev. 3.0, 09/98, page 246 of 36112.2 Register Descriptions12.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) H'FFA8, H'FFA9Bit:76543210Initial

Rev. 3.0, 09/98, page 247 of 361Bit 6D/A Output Enable 0 (DAOE0): Controls analog output from the D/A converter.Bit 6DAOE0 Description0 Analog outpu

Rev. 3.0, 09/98, page 248 of 36112.3 OperationThe D/A converter module has two built-in D/A converter circuits that can operate independently.D/A conv

Rev. 3.0, 09/98, page 249 of 361Section 13 RAM13.1 OverviewThe H8/338 includes 2k bytes of on-chip static RAM. The H8/337 and H8/336 have 1k byte.

Rev. 3.0, 09/98, page 250 of 36113.3 RAM Enable Bit (RAME) in System Control Register (SYSCR)The on-chip RAM is enabled or disabled by the RAME (RAM E

Rev. 3.0, 09/98, page 15 of 361Section 2 CPU2.1 OverviewThe H8/338 Series has the H8/300 CPU: a fast central processing unit with eight 16-bit gener

Rev. 3.0, 09/98, page 251 of 361Section 14 ROM14.1 OverviewThe H8/338 includes 48k bytes of high-speed, on-chip ROM. The H8/337 has 32k bytes. The

Rev. 3.0, 09/98, page 252 of 36114.1.1 Block DiagramFigure 14.1 is a block diagram of the on-chip ROM.Internal data bus (upper 8 bits)Internal data bu

Rev. 3.0, 09/98, page 253 of 36114.2.2 Socket Adapter Pin Assignments and Memory MapThe H8/338 and H8/337 can be programmed with a general-purpose PRO

Rev. 3.0, 09/98, page 254 of 361 1 6656667686970717264636261605958575554535251504948201918242529 847 5 4 738125673————CG-84, CP-84 PinRESNMIP3P3

Rev. 3.0, 09/98, page 255 of 361On-chipPROMUndeterminedoutput*Address in MCU mode Address in PROM modeH'0000H'0000H'BFFFH'1FFFFH&a

Rev. 3.0, 09/98, page 256 of 361On-chipPROMUndeterminedoutput*Address in MCU mode Address in PROM modeH'0000H'0000H'7FFFH'1FFFFH&a

Rev. 3.0, 09/98, page 257 of 36114.3 ProgrammingThe write, verify, and other sub-modes of the PROM mode are selected as shown in table 14.4.Table 14.4

Rev. 3.0, 09/98, page 258 of 361STARTSet read modeVCC = 5.0V ±0.25V, VPP = VCCSet program/verify modeVCC = 6.0V ±0.25V, VPP = 12.5V ±0.3VAddress = 0n

Rev. 3.0, 09/98, page 259 of 361Table 14.5 DC Characteristics(when VCC = 6.0V ±0.25V, VPP = 12.5V ±0.3V, VSS = 0V, Ta = 25°C ±5°C)Item Symbol Min Typ

Rev. 3.0, 09/98, page 260 of 361Table 14.6. AC Characteristics (cont)(when VCC = 6.0V ±0.25V, VPP = 12.5V ±0.3V, Ta = 25°C ±5°C)Item Symbol Min Typ Ma

Rev. 3.0, 09/98, page 16 of 3612.2 Register ConfigurationFigure 2.1 shows the register structure of the CPU. There are two groups of registers: the

Rev. 3.0, 09/98, page 261 of 36114.3.2 Notes on Writing(1) Write with the specified voltages and timing. The programming voltage (VPP) is 12.5V.Caut

Rev. 3.0, 09/98, page 262 of 36114.3.3 Reliability of Written DataAn effective way to assure the data holding characteristics of the programmed chips

Rev. 3.0, 09/98, page 263 of 36114.3.4 Erasing of DataThe windowed package enables data to be erased by illuminating the window with ultravioletlight.

Rev. 3.0, 09/98, page 264 of 361(3) Note on 84-Pin LCC Package: A socket should always be used when the 84-pin LCCpackage is mounted on a printed-ci

Rev. 3.0, 09/98, page 265 of 361Section 15 Power-Down State15.1 OverviewThe H8/338 Series has a power-down state that greatly reduces power consumpt

Rev. 3.0, 09/98, page 266 of 36115.2 System Control Register: Power-Down Control BitsBits 7 to 4 of the system control register (SYSCR) concern the p

Rev. 3.0, 09/98, page 267 of 361When the on-chip clock pulse generator is used, the STS bits should be set to allow a settling timeof at least 10ms.

Rev. 3.0, 09/98, page 268 of 36115.3 Sleep ModeThe sleep mode provides an effective way to conserve power while the CPU is waiting for anexternal inte

Rev. 3.0, 09/98, page 269 of 36115.4 Software Standby ModeIn the software standby mode, the system clock stops and chip functions halt, including both

Rev. 3.0, 09/98, page 270 of 36115.4.3 Sample Application of Software Standby ModeIn this example the chip enters the software standby mode when NMI g

Rev. 3.0, 09/98, page 17 of 3612.2.1 General RegistersAll the general registers can be used as both data registers and address registers. When used a

Rev. 3.0, 09/98, page 271 of 36115.4.4 Application Note1. The I/O ports retain their current states in the software standby mode. If a port is in the

Rev. 3.0, 09/98, page 272 of 36115.5 Hardware Standby Mode15.5.1 Transition to Hardware Standby ModeRegardless of its current state, the chip enters t

Rev. 3.0, 09/98, page 273 of 361Clock pulsegeneratorRESSTBYRestartClock settlingtimeFigure 15.2 Hardware Standby Mode Timing

Rev. 3.0, 09/98, page 275 of 361Section 16 Electrical Specifications16.1 Absolute Maximum RatingsTable 16.1 lists the absolute maximum ratings.Table

Rev. 3.0, 09/98, page 276 of 361Table 16.2 DC Characteristics (5V version)Conditions: VCC = 5.0V ±10%, AVCC = 5.0V ±10%*, VSS = AVSS = 0V,Ta = −20 to

Rev. 3.0, 09/98, page 277 of 361Table 16.2 DC Characteristics (5V version) (cont)Conditions: VCC = AVCC = 5.0V ±10%, VSS = AVSS = 0V,Ta = −20 to 75°C

Rev. 3.0, 09/98, page 278 of 361Table 16.3 DC Characteristics (3V version)Conditions: VCC = 3.0V ±10%, AVCC = 5.0V ±10%*1, VSS = AVSS = 0V, Ta = −20 t

Rev. 3.0, 09/98, page 279 of 361Table 16.3 DC Characteristics (3V version) (cont)Conditions: VCC = 3.0V ±10%, AVCC = 5.0V ±10%*1, VSS = AVSS = 0V, Ta

Rev. 3.0, 09/98, page 280 of 361Table 16.4 Allowable Output Current Values (5V version)Conditions: VCC = AVCC = 5.0V ±10%, VSS = AVSS = 0V,Ta = −20 to

Rev. 3.0, 09/98, page 281 of 361H8/338DarlingtonpairPort2 kFigure 16.1 Example of Circuit for Driving a Darlington Pair (5V Version)H8/338Port 1 or

Rev. 3.0, 09/98, page 18 of 361“0” otherwise. Similarly, it is set to “1” when the ADD.W, SUB.W, or CMP.W instruction causesa carry or borrow out of

Rev. 3.0, 09/98, page 282 of 361Table 16.6 Bus TimingCondition A: VCC = 5.0V ±10%, VSS = 0V, φ = 0.5MHz to maximum operating frequency,Ta = −20 to 75°

Rev. 3.0, 09/98, page 283 of 361Table 16.7 Control Signal TimingCondition A: VCC = 5.0V ±10%, VSS = 0V, φ = 0.5MHz to maximum operating frequency,Ta =

Rev. 3.0, 09/98, page 284 of 361Table 16.8 Timing Conditions of On-Chip Supporting ModulesCondition A: VCC = 5.0V ±10%, VSS = 0V, φ = 0.5MHz to maximu

Rev. 3.0, 09/98, page 285 of 361Table 16.8 Timing Conditions of On-Chip Supporting Modules (cont)Condition A: VCC = 5.0V ±10%, VSS = 0V, φ = 0.5MHz to

Rev. 3.0, 09/98, page 286 of 36116.2.3 A/D Converter CharacteristicsTable 16.9 lists the characteristics of the on-chip A/D converter.Table 16.9 A/D C

Rev. 3.0, 09/98, page 287 of 36116.2.4 D/A Converter CharacteristicsTable 16.10 lists the characteristics of the on-chip D/A converter.Table 16.10 D/A

Rev. 3.0, 09/98, page 288 of 36116.3.1 Bus Timing(1) Basic Bus Cycle (without Wait States) in Expanded ModesØA15 + A0AS, RDD7 to D0(Read)D7 to D0(Wri

Rev. 3.0, 09/98, page 289 of 361(2) Basic Bus Cycle (with 1 Wait State) in Expanded ModesØA15 + A0AS, RDD7 to D0(Read)D7 to D0(Write)WRT1WAITT2 TW T3

Rev. 3.0, 09/98, page 290 of 36116.3.2 Control Signal Timing(1) Reset Input TimingØREStRESStRESStRESWFigure 16.6 Reset Input Timing(2) Interrupt I

Rev. 3.0, 09/98, page 291 of 361(3) Clock Settling TimingØRESSTBYVCCtOSC1tOSC1Figure 16.8 Clock Settling Timing(4) Clock Settling Timing for Recov

Cautions1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’spatent, copyright, trademark, or other intellec

Rev. 3.0, 09/98, page 19 of 3612.3 Addressing Modes2.3.1 Addressing ModeThe H8/300 CPU supports eight addressing modes. Each instruction uses a subse

Rev. 3.0, 09/98, page 292 of 36116.3.3 16-Bit Free-Running Timer Timing(1) Free-Running Timer Input/Output TimingØFree-runningtimer counterCompare-ma

Rev. 3.0, 09/98, page 293 of 36116.3.4 8-Bit Timer Timing(1) 8-Bit Timer Output TimingØTimercounterCompare-matchTMC0,TMC1tTMODFigure 16.12 8-Bit Ti

Rev. 3.0, 09/98, page 294 of 36116.3.5 Pulse Width Modulation Timer TimingØTimercounterCompare-matchPW0, PW1tPWODFigure 16.15 PWM Timer Output Timin

Rev. 3.0, 09/98, page 295 of 36116.3.7 I/O Port TimingtPRHØPort 1 to Port 9(Input)Port 1* to Port 9(Output)T1T2tPRStPWDT3Note: * Except P96 and P77 to

Rev. 3.0, 09/98, page 297 of 361Appendix A CPU Instruction SetA.1 Instruction Set ListOperation NotationRd8/16 General register (destination) (8 or

Rev. 3.0, 09/98, page 298 of 361Table A.1 Instruction SetMnemonic OperationAddressing Mode/Instruction LengthOperand Size#xx: 8/16Rn@Rn@(d:16, Rn)@–Rn

Rev. 3.0, 09/98, page 299 of 361Table A.1 Instruction Set (cont)Mnemonic OperationAddressing Mode/Instruction LengthOperand Size#xx: 8/16Rn@Rn@(d:16,

Rev. 3.0, 09/98, page 300 of 361Table A.1 Instruction Set (cont)Mnemonic OperationAddressing Mode/Instruction LengthOperand Size#xx: 8/16Rn@Rn@(d:16,

Rev. 3.0, 09/98, page 301 of 361Table A.1 Instruction Set (cont)Mnemonic OperationAddressing Mode/Instruction LengthOperand Size#xx: 8/16Rn@Rn@(d:16,

Rev. 3.0, 09/98, page 302 of 361Table A.1 Instruction Set (cont)Mnemonic OperationAddressing Mode/Instruction LengthOperand Size#xx: 8/16Rn@Rn@(d:16,

Rev. 3.0, 09/98, page 20 of 361• Register Indirect with Pre-Decrement@−RnThe @−Rn mode is used with MOV instructions that store register contents to

Rev. 3.0, 09/98, page 303 of 361Table A.1 Instruction Set (cont)Mnemonic OperationAddressing Mode/Instruction LengthOperand Size#xx: 8/16Rn@Rn@(d:16,

Rev. 3.0, 09/98, page 304 of 361Table A.1 Instruction Set (cont)Mnemonic OperationAddressing Mode/Instruction Length (Bytes)Operand Size#xx: 8/16Rn@Rn

Rev. 3.0, 09/98, page 305 of 361A.2 Operation Code MapTable A.2 is a map of the operation codes contained in the first byte of the instruction code (b

Rev. 3.0, 09/98, page 306 of 361Table A.2 Operation Code MapHighLow0123456789ABCDEF0123456789ABCDEFNOPBRAMULXUBSETSHLLSHALSLEEPBRN DIVXUBNOTSHLRSHARST

Rev. 3.0, 09/98, page 307 of 361A.3 Number of States Required for ExecutionThe tables below can be used to calculate the number of states required for

Rev. 3.0, 09/98, page 308 of 361Table A.4 Number of Cycles in Each InstructionInstruction MnemonicInstructionFetchIBranchAddr. ReadJStackOperationKByt

Rev. 3.0, 09/98, page 309 of 361Table A.4 Number of Cycles in Each Instruction (cont)Instruction MnemonicInstructionFetchIBranchAddr. ReadJStackOperat

Rev. 3.0, 09/98, page 310 of 361Table A.4 Number of Cycles in Each Instruction (cont)Instruction MnemonicInstructionFetchIBranchAddr. ReadJStackOperat

Rev. 3.0, 09/98, page 311 of 361Table A.4 Number of Cycles in Each Instruction (cont)Instruction MnemonicInstructionFetchIBranchAddr. ReadJStackOperat

Rev. 3.0, 09/98, page 312 of 361Table A.4 Number of Cycles in Each Instruction (cont)Instruction MnemonicInstructionFetchIBranchAddr. ReadJStackOperat

Rev. 3.0, 09/98, page 21 of 3612.3.2 How to Calculate Where the Execution StartsTable 2.2 shows how to calculate the Effective Address (EA: Effective

Rev. 3.0, 09/98, page 313 of 361Appendix B Register FieldB.1 Register Addresses and Bit NamesBit NamesAddr.(lastbyte)RegisterNameBit 7 Bit 6 Bit 5 B

Rev. 3.0, 09/98, page 314 of 361Bit NamesAddr.(lastbyte)RegisterNameBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ModuleH'A0 TCR OE OSCKS2 C

Rev. 3.0, 09/98, page 315 of 361Bit NamesAddr.(lastbyte)RegisterNameBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ModuleH'C0 P9DDR P97DDR P96DD

Rev. 3.0, 09/98, page 316 of 361Bit NamesAddr.(lastbyte)RegisterNameBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ModuleH'E0 ADDRA A/DH'E1

Rev. 3.0, 09/98, page 317 of 361B.2 Register Descriptions7ICIAE0R/WBitInitial valueRead/Write6ICIBE0R/W5ICICE0R/W4ICIDE0R/WOverflow Interrupt EnableOv

Rev. 3.0, 09/98, page 318 of 361SMRSerial Mode Register H'FF88 SCI1BitInitial valueRead/Write7C/A0R/W6CHR0R/W5PE0R/W0CKS00R/W2MP0R/W1CKS10R/W4O/

Rev. 3.0, 09/98, page 319 of 361BRRBit Rate Register H'FF89 SCI1BitInitial valueRead/Write71R/W61R/W51R/W41R/W31R/W01R/W21R/W11R/WConstant that

Rev. 3.0, 09/98, page 320 of 361SCRSerial Control Register H'FF8A SCI1BitInitial valueRead/Write7TIE0R/W6RIE0R/W5TE0R/W4RE0R/W3MPIE0R/W0CKE01R/W

Rev. 3.0, 09/98, page 321 of 361TDRTransmit Data Register H'FF8B SCI1BitInitial valueRead/Write71R/W61R/W51R/W41R/W31R/W01R/W21R/W11R/WTransmit

Rev. 3.0, 09/98, page 322 of 361SSRSerial Status Register H'FF8C SCI1BitInitial valueRead/WriteNote: * Software can write a “0” in bits 7 to 3

Rev. 3.0, 09/98, page 22 of 361Table 2.2 Effective Address CalculationAddressing mode andinstruction formatop reg76 34015 No. Effective address calcul

Rev. 3.0, 09/98, page 323 of 361RDRReceive Data Register H'FF8D SCI1BitInitial valueRead/Write70R60R50R40R30R00R20R10RReceive data

Rev. 3.0, 09/98, page 324 of 361TIERTimer Interrupt Enable Register H'FF90 FRTBitInitial valueRead/Write7ICIAE0R/W6ICIBE0R/W5ICICE0R/W4ICIDE0R/W

Rev. 3.0, 09/98, page 325 of 361TCSRTimer Control/Status Register H'FF91 FRTBitInitial valueRead/Write7ICFA0R/(W)6ICFB0R/(W)5ICFC0R/(W)4ICFD0R/(

Rev. 3.0, 09/98, page 326 of 361FRC (H and L)Free-Running Counter H'FF92, H'FF93 FRTBitInitial valueRead/Write70R/W60R/W50R/W40R/W30R/W00R/

Rev. 3.0, 09/98, page 327 of 361TCRTimer Control Register H'FF96 FRTBitInitial valueRead/Write7IEDGA0R/W6IEDGB0R/W5IEDGC0R/W4IEDGD0R/W3BUFEA0R/W

Rev. 3.0, 09/98, page 328 of 361TOCRTimer Output Compare Control Register H'FF97 FRTBitInitial valueRead/Write7—1—6—1—5—1—4OCRS0R/W3OEA0R/W0OLVL

Rev. 3.0, 09/98, page 329 of 361ICRB (H and L)Input Capture Register B H'FF9A, H'FF9B FRTBitInitial valueRead/Write70R60R50R40R30R00R20R10R

Rev. 3.0, 09/98, page 330 of 361TCRTimer Control Register H'FFA0 PWM0BitInitial valueRead/Write7OE0R/W6OS0R/W5—1—4—1—3—1—0CKS00R/W2CKS20R/W1CKS1

Rev. 3.0, 09/98, page 331 of 361TCNTTimer Counter H'FFA2 PWM0BitInitial valueRead/Write70R/W60R/W50R/W40R/W30R/W00R/W20R/W10R/WCount value (runs

Rev. 3.0, 09/98, page 332 of 361TCNTTimer Counter H'FFA6 PWM1BitInitial valueRead/Write70R/W60R/W50R/W40R/W30R/W00R/W20R/W10R/WNote: Bit functio

Rev. 3.0, 09/98, page 23 of 361Table 2.2 Effective Address Calculation (cont)Addressing mode andinstruction format No. Effective address calculation E

Rev. 3.0, 09/98, page 333 of 361DACRD/A Control Register H'FFAA D/ABitInitial valueRead/Write7DAOE10R/W6DAOE00R/W5DAE0R/W4—1—3—1—0—1—2—1—1—1—DAO

Rev. 3.0, 09/98, page 334 of 361P2PCRPort 2 Input Pull-Up Control Register H'FFAD Port 2BitInitial valueRead/Write7P27PCR0R/W6P26PCR0R/W5P25PCR0

Rev. 3.0, 09/98, page 335 of 361P1DDRPort 1 Data Direction Register H'FFB0 Port 1BitMode 1 Initial value Read/WriteModes 2 and 3 Initial valu

Rev. 3.0, 09/98, page 336 of 361P2DDRPort 2 Data Direction Register H'FFB1 Port 2BitMode 1 Initial value Read/WriteModes 2 and 3 Initial valu

Rev. 3.0, 09/98, page 337 of 361P3DRPort 3 Data Register H'FFB6 Port 3BitInitial valueRead/Write7P370R/W6P360R/W5P350R/W4P340R/W3P330R/W0P300R/W

Rev. 3.0, 09/98, page 338 of 361P5DRPort 5 Data Register H'FFBA Port 5BitInitial valueRead/Write7—1—6—1—5—1—4—1—3—1—0P500R/W2P520R/W1P510R/WP6DD

Rev. 3.0, 09/98, page 339 of 361P8DDRPort 8 Data Direction Register H'FFBD Port 8BitInitial valueRead/Write7—1—6P86DDR0W5P85DDR0W4P84DDR0W3P83DD

Rev. 3.0, 09/98, page 340 of 361P9DRPort 9 Data Register H'FFC1 Port 9BitInitial valueRead/WriteNotes: * Depends on the level of pin P96.7P960R/

Rev. 3.0, 09/98, page 341 of 361SYSCRSystem Control Register H'FFC4 System ControlBitInitial valueRead/Write7SSBY0R/W6STS20R/W5STS10R/W4STS00R/W

Rev. 3.0, 09/98, page 342 of 361MDCRMode Control Register H'FFC5 System ControlBitInitial valueRead/WriteNote: * Determined by inputs at pins MD

Rev. 3.0, 09/98, page 24 of 361Table 2.2 Effective Address Calculation (cont)Table 3-2. Effective Address Calculation (3)Addressing mode andinstructi

Rev. 3.0, 09/98, page 343 of 361TCRTimer Control Register H'FFC8 TMR0BitInitial valueRead/Write7CMIEB0R/W6CMIEA0R/W5OVIE0R/W4CCLR10R/W3CCLR00R/W

Rev. 3.0, 09/98, page 344 of 361TCSRTimer Control/Status Register H'FFC9 TMR0BitInitial valueRead/Write7CMFB0R/(W)*16CMFA0R/(W)*15OVF0R/(W)*14—1

Rev. 3.0, 09/98, page 345 of 361TCORATime Constant Register A H'FFCA TMR0BitInitial valueRead/Write71R/W61R/W51R/W41R/W31R/W01R/W21R/W11R/WThe C

Rev. 3.0, 09/98, page 346 of 361TCRTimer Conrol Register H'FFD0 TMR1BitInitial valueRead/Write7CMIEB0R/W6CMIEA0R/W5OVIE0R/W4CCLR10R/W3CCLR00R/W0

Rev. 3.0, 09/98, page 347 of 361TCSRTimer Control/Status Register H'FFD1 TMR1BitInitial valueRead/Write7CMFB0R/(W)*16CMFA0R/(W)*15OVF0R/(W)*14—1

Rev. 3.0, 09/98, page 348 of 361SMRSerial Mode Register H'FFD8 SCI0BitInitial valueRead/Write7C/A0R/W6CHR0R/W5PE0R/W0CKS00R/W2MP0R/W1CKS10R/W4O/

Rev. 3.0, 09/98, page 349 of 361BRRBit Rate Register H'FFD9 SCI0BitInitial valueRead/WriteNote: Bit functions are the same as for SCI1.71R/W61R/

Rev. 3.0, 09/98, page 350 of 361SCRSerial Control Register H'FFDA SCI0BitInitial valueRead/Write7TIE0R/W6RIE0R/W5TE0R/W4RE0R/W3MPIE0R/W0CKE00R/W

Rev. 3.0, 09/98, page 351 of 361TDRTransmit Data Register H'FFDB SCI0BitInitial valueRead/WriteNote: Bit functions are the same as for SCI1.71R/

Rev. 3.0, 09/98, page 352 of 361SSRSerial Status Register H'FFDC SCI0BitInitial valueRead/WriteNote: Software can write a “0” in bits 7 to 3 to

Rev. 3.0, 09/98, page 25 of 3612.4 Data FormatsThe H8/300 CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word)data.• Bit

Rev. 3.0, 09/98, page 353 of 361RDRReceive Data Register H'FFDD SCI0BitInitial valueRead/WriteNote: Bit functions are the same as for SCI1.70R60

Rev. 3.0, 09/98, page 354 of 361ADCSRA/D Control/Status Register H'FFE8 A/DBitInitial valueRead/Write7ADF0R/(W)*6ADIE0R/W5ADST0R/W4SCAN0R/W3CKS0

Rev. 3.0, 09/98, page 355 of 361ADCRA/D Control Register H'FFEA A/DBitInitial valueRead/Write7TRGE0R/W6—1—5—1—4—1—3—1—0CHS0R/W2—1—1—1—Trigger En

Rev. 3.0, 09/98, page 356 of 361Appendix C Pin StatesC.1 Pin States in Each ModeTable C.1 Pin StatesPin NameMCUMode ResetHardwareStandbySoftwareStan

Rev. 3.0, 09/98, page 357 of 361Table C.1 Pin States (cont)Pin NameMCUMode ResetHardwareStandbySoftwareStandby Sleep ModeNormalOperationP67 − P601233-

Rev. 3.0, 09/98, page 358 of 361Appendix D Timing of Transition to and Recovery fromHardware Standby ModeTiming of Transition to Hardware Standby Mo

Rev. 3.0, 09/98, page 359 of 361Appendix E Package DimensionsFigure E.1 shows the dimensions of the CG-84 package. Figure E.2 shows the dimensions

Rev. 3.0, 09/98, page 360 of 3611.27 *0.42 ± 0.1029.28 28.20 ± 0.5028.20 ± 0.504.40 ± 0.202.55 ± 0.150.1053335474758411112320.7530.23+0.12–0.1330.23+0

Rev. 3.0, 09/98, page 361 of 361Hitachi CodeJEDECEIAJWeight (reference value)FP-80A—Conforms 1.2 gUnit: mm*Dimension including the plating thicknessBa

H8/338 Series Hardware ManualPublication Date: 1st Edition, July 19923rd Edition, September 1998Published by: Electronic Devices Sales & Marketing

Rev. 3.0, 09/98, page 26 of 3612.4.1 Data Formats in General RegistersData of all the sizes above can be stored in general registers as shown in figur

Rev. 3.0, 09/98, page 27 of 3612.4.2 Memory Data FormatsFigure 2.4 indicates the data formats in memory.Word data stored in memory must always begin a

Rev. 3.0, 09/98, page 28 of 3612.5 Instruction SetTable 2.3 lists the H8/300 instruction set.Table 2.3 Instruction ClassificationFunction Instructions

Rev. 3.0, 09/98, page i of viiiPrefaceThe H8/338 Series is a series of high-performance single-chip microcomputers having a fastH8/300 CPU core and a

Rev. 3.0, 09/98, page 29 of 361Operation NotationRd General register (destination)Rs General register (source)Rn General register(EAd) Destination o

Rev. 3.0, 09/98, page 30 of 3612.5.1 Data Transfer InstructionsTable 2.4 describes the data transfer instructions. Figure 2.5 shows their object code

Rev. 3.0, 09/98, page 31 of 361Rm Rn0MOV7815Op rmrnRn @Rm, or @Rm RnOp rnrm@(d:16, Rm) Rn,orRn @(d:16, Rm)Op rnrmdisp.@Rm+ R

Rev. 3.0, 09/98, page 32 of 3612.5.2 Arithmetic OperationsTable 2.5 describes the arithmetic instructions. See figure 2.6 in section 2.5.4, “Shift Op

Rev. 3.0, 09/98, page 33 of 3612.5.3 Logic OperationsTable 2.6 describes the four instructions that perform logic operations. See figure 2.6 in secti

Rev. 3.0, 09/98, page 34 of 361ADD, AUB, CMPADDX, SUBX(Rm), MULXU, DIVXU07815Op rm rnADDS, SUBS, INC, DEC, DAA,DAS, NEG, NOTOp rnADD, ADDX, SUBX, CMP(

Rev. 3.0, 09/98, page 35 of 3612.5.5 Bit ManipulationsTable 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code forma

Rev. 3.0, 09/98, page 36 of 361Table 2.8 Bit-Manipulation Instructions (cont)Instruction Size*FunctionBIXOR BC ⊕ ¬ [(<bit-No.> of <EAd>)]

Rev. 3.0, 09/98, page 37 of 361Before Execution of BCLR InstructionP47P46P45P44P43P42P41P40Input/output Input Input Output Output Output Output Output

Rev. 3.0, 09/98, page 38 of 361Operand: register direct (Rn)Bit No.: immediate (#xx:3)0 BSET, BCLR, BNOT, BTST7815Op #imm. rnOperand: register direc

Rev. 3.0, 09/98, page ii of viiiContentsSection 1 Overview...

Rev. 3.0, 09/98, page 39 of 3612.5.6 Branching InstructionsTable 2.9 describes the branching instructions. Figure 2.8 shows their object code formats

Rev. 3.0, 09/98, page 40 of 361BCC07815OpCCdisp.JMP(@Rm)Op rm0000JSR(@Rm)Op rm0000JMP(@@aa:8)Op abs.JSR(@@aa:8)Op abs.RTSOpBSROp disp.JMP(@aa:16)Opabs

Rev. 3.0, 09/98, page 41 of 3612.5.7 System Control InstructionsTable 2.10 describes the system control instructions. Figure 2.9 shows their object c

Rev. 3.0, 09/98, page 42 of 361RTE, SLEEP, NOP07815OpLDC, STC(Rn)Op rnANDC, ORC, XORC, LDC(#XX:8)Op #imm.Oprn#imm.: Operation field: Register field: i

Rev. 3.0, 09/98, page 43 of 361Op8715 0EEPROMOp: Operation fieldOpFigure 2.10 Block Data Transfer Instruction/EEPROM Write Operation CodeNotes on EE

Rev. 3.0, 09/98, page 44 of 3612.6 CPU StatesThe CPU has three states: the program execution state, exception-handling state, and power-downstate. T

Rev. 3.0, 09/98, page 45 of 361Programexecution stateException-handling stateInterrupt requestNMI or IRQ0to IRQ2SLEEP instructionwith SSBY bit setSLEE

Rev. 3.0, 09/98, page 46 of 3612.6.3 Power-Down StateThe power-down state includes three modes: the sleep mode, the software standby mode, and thehar

Rev. 3.0, 09/98, page 47 of 3612.7 Access Timing and Bus CycleThe CPU is driven by the system clock (φ). The period from one rising edge of the syste

Rev. 3.0, 09/98, page 48 of 361ØAddress busRD: HighData bus:high impedance stateAS: HighWR: HighBus cycleT1 state T2 stateAddressFigure 2.14 Pin Sta

Rev. 3.0, 09/98, page iii of viii3.2 System Control Register (SYSCR)H'FFC4... 54

Rev. 3.0, 09/98, page 49 of 3612.7.2 Access to On-Chip Register Field and External DevicesThe on-chip register field (I/O ports, dual-port RAM, on-chi

Rev. 3.0, 09/98, page 50 of 361ØAddress busAS: HighRD: HighWR: HighData bus:high impedance stateBus cycleT1 state T2 stateAddressT3 stateFigure 2.16

Rev. 3.0, 09/98, page 51 of 361Address busASRDWR: HighData busRead cycleT1 state T2 stateAddressT3 stateRead dataØFigure 2.17 (a) External Device Ac

Rev. 3.0, 09/98, page 52 of 361Address busASWRRD: HighData busWrite cycleT1 state T2 stateWrite dataAddressT3 stateØFigure 2.17 (b) External Device

Rev. 3.0, 09/98, page 53 of 361Section 3 MCU Operating Modes and Address Space3.1 Overview3.1.1 Mode SelectionThe H8/338 Series operates in three mo

Rev. 3.0, 09/98, page 54 of 3613.1.2 Mode and System Control Registers (MDCR and SYSCR)Table 3.2 lists the registers related to the chip’s operating m

Rev. 3.0, 09/98, page 55 of 361Bits 6 to 4Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settlingtime when the chip recover

Rev. 3.0, 09/98, page 56 of 3613.3 Mode Control Register (MDCR)H'FFC5Bit:76543210MDS1 MDS0Initial value:111001**Read/Write: R R R R R R R

Rev. 3.0, 09/98, page 57 of 3613.4 Address Space MapFigures 3.1 to 3.3 show memory maps of the H8/338, H8/337, and H8/336 in modes 1, 2, and 3.H'

Rev. 3.0, 09/98, page 58 of 361H'FFFFH'FF88H'FF87H'FF80H'FF7FH'FB80H'FB7FH'F780H'F77FH'0048H'00

Rev. 3.0, 09/98, page iv of viii7.1.3 Input and Output Pins...

Rev. 3.0, 09/98, page 59 of 361H'FFFFH'FF88H'FF87H'FF80H'FF7FH'FB80H'FB7FH'F780H'F77FH'0048H'00

Rev. 3.0, 09/98, page 61 of 361Section 4 Exception Handling4.1 OverviewThe H8/338 Series recognizes only two kinds of exceptions: interrupts and the

Rev. 3.0, 09/98, page 62 of 361Figure 4.1 indicates the timing of the reset sequence in modes 2 and 3. Figure 4.2 indicates thetiming in mode 1.Inter

Rev. 3.0, 09/98, page 63 of 361A15 to A0RDWRD7 to D0(8 bits)ØRES(2) (4) (6) (8)(1)Vector fetch(1),(3) Reset vector address: (1)=H'0000, (3)=H&apo

Rev. 3.0, 09/98, page 64 of 3614.2.3 Disabling of Interrupts after ResetAfter a reset, if an interrupt were to be accepted before initialization of th

Rev. 3.0, 09/98, page 65 of 361Table 4.2 InterruptsInterrupt source No.Address of Entry inVector Table PriorityNMIIRQ0IRQ1IRQ2IRQ3IRQ4IRQ5IRQ6IRQ73456

Rev. 3.0, 09/98, page 66 of 3614.3.2 Interrupt-Related RegistersThe interrupt-related registers are the system control register (SYSCR), IRQ sense con

Rev. 3.0, 09/98, page 67 of 361Bits 0 to 7IRQ0 to IRQ7 Sense Control (IRQ0SC to IRQ7SC): These bits determine whetherIRQ0 to IRQ7 are level-sensed o

Rev. 3.0, 09/98, page 68 of 3614.3.3 External InterruptsThe nine external interrupts are NMI and IRQ0 to IRQ7. NMI, IRQ0, IRQ1, and IRQ2 can be usedt

Rev. 3.0, 09/98, page 69 of 361IRQ flagIRQ 0EADFADIECPUI (CCR)NMI interruptInterrupt controllerIRQ0interruptInterrupt requestVector numberADIinterrupt

Rev. 3.0, 09/98, page v of viiiSection 9 PWM Timers...

Rev. 3.0, 09/98, page 70 of 361(1) An interrupt request is sent to the interrupt controller when an NMI interrupt occurs, and whenan interrupt occurs

Rev. 3.0, 09/98, page 71 of 361Program executionNoNoNoYesNoYesYesYesNoYesNMI?I = 0?IRQ 0?IRQ 1?ADI?ResetI 1Interruptrequested?PendingLatch vector No.S

Rev. 3.0, 09/98, page 72 of 361SP-4SP-3SP-2SP-1SP(R7)Stack areaSP(R7)SP+1SP+2SP+3SP+4 Even addressAfter interruptis acceptedPushed onto stackBefore in

Rev. 3.0, 09/98, page 73 of 361Internal addressbusInternal ReadsignalInternal WritesignalInternal 16-bitdata busØInterrupt requestsignal(2) (4) (1) (7

Rev. 3.0, 09/98, page 74 of 3614.3.6 Interrupt Response TimeTable 4.4 indicates the number of states that elapse from an interrupt request signal unti

Rev. 3.0, 09/98, page 75 of 3614.3.7 PrecautionNote that the following type of contention can occur in interrupt handling.Contention between Interrupt

Rev. 3.0, 09/98, page 76 of 3614.4 Note on Stack HandlingIn word access, the least significant bit of the address is always assumed to be 0. The stac

Rev. 3.0, 09/98, page 77 of 361Section 5 Clock Pulse Generator5.1 OverviewThe H8/338 Series has a built-in clock pulse generator (CPG) consisting of

Rev. 3.0, 09/98, page 78 of 3615.2 Oscillator CircuitIf an external crystal is connected across the EXTAL and XTAL pins, the on-chip oscillator circui

Rev. 3.0, 09/98, page 79 of 361③③ Note on Board Design: When an external crystal is connected, other signal lines should bekept away from the crystal

Rev. 3.0, 09/98, page vi of viii11.2 Register Descriptions ...

Rev. 3.0, 09/98, page 80 of 361(2) Input of External Clock Signal①① Circuit Configuration: An external clock signal can be input as shown in the exa

Rev. 3.0, 09/98, page 81 of 361Section 6 I/O Ports6.1 OverviewThe H8/338 Series has nine parallel I/O ports, including:• Six 8-bit input/output port

Rev. 3.0, 09/98, page 82 of 361Table 6.1 Port FunctionsExpanded ModesSingle-ChipModePort Description Pins Mode 1 Mode 2 Mode 3Port 1• 8-bit input-outp

Rev. 3.0, 09/98, page 83 of 361Table 6.1 Port Functions (cont)Expanded ModesSingle-ChipModePort Description Pins Mode 1 Mode 2 Mode 3Port 7• 8-bit inp

Rev. 3.0, 09/98, page 84 of 3616.2 Port 1Port 1 is an 8-bit input/output port that also provides the low bits of the address bus. The functionof port

Rev. 3.0, 09/98, page 85 of 361Port 1 Data Register (P1DR)H'FFB2Bit:76543210P17P16P15P14P13P12P11P10Initial value:00000000Read/Write: R/W R/W R/

Rev. 3.0, 09/98, page 86 of 361Input Pull-Up Transistors: Port 1 has built-in programmable input pull-up transistors that areavailable in modes 2 and

Rev. 3.0, 09/98, page 87 of 361Figure 6.1 shows a schematic diagram of port 1.P1nHardware standbyMode 3Mode 1 or 2RP1ResetResetMode 1ResetWP1WP1DWP1PR

Rev. 3.0, 09/98, page 88 of 3616.3 Port 2Port 2 is an 8-bit input/output port that also provides the high bits of the address bus. The functionof por

Rev. 3.0, 09/98, page 89 of 361Port 2 Data Register (P2DR)H'FFB3Bit:76543210P27P26P25P24P23P22P21P20Initial value:00000000Read/Write: R/W R/W R/