Renesas Single-Chip Microcomputer M34519T-MCU Specifikace stáhnout pdf (Strana 13)

38 MIPS @ 33 MHz

43 MIPS @ 20 MHz

23 MIPS @ 20 MHz

142 MIPS @ 66 MHz

215 MIPS @ 100 MHz

V850E2 CPU

432 MIPS @ 200 MHz

V850E2M CPU

512 MIPS @ 200 MHz

V850E2M

dual CPU

V850 CPU

V850ES CPU

V850E1 CPU

V850E2 CPU

323 MIPS @ 150 MHz

69 MIPS @ 32 MHz

98 MIPS @ 48 MHz

103 MIPS @ 50 MHz

V850 Next

Performance of

20 to over 500 MIPS

using a single instruction set

• Can use existing software resources

• Maintain a real-time performance

• Lower power consumption

V850E2 V850E2M

Characteristics

CPU

Improved pipeline

• Non-blocking load/store instructions

Parallel instruction execution (instruction execution in internal ROM)

• Addition of branching/load pipe

• Shift to 3-operand manipulations in 1 slot

Addition of C language compatible instructions

(Switch instruction, Callt instruction,

data conversion instruction,

Prepare/Dispose instruction)

32-bit relative branch instruction

3-operand instruction

Sum-of-products instruction

Bit search instruction

16 × 16 bits ⇒ 32-bit operation

32 × 32 bits ⇒ 64-bit operation

(32-bit multiply instruction support)

16 × 16 bits ⇒ 32-bit operation

32 × 32 bits ⇒ 64-bit operation

4 to 10 clocks

−

• 7-stage pipeline

Simultaneous execution

of 2 instructions

Optimized instruction execution

Enhanced ability to execute 2 instructions simultane-

ously

Can be used with a single-precision or double-precision high-speed

FPU

V850

20/33 MHz

16 MB

11 to 18 clocks

16 MB

V850ES

20/32/48/50 MHz

16 MB

V850E1

66 ⇒ 100 ⇒ 150 MHz

64 MB

256 MB

200 MHz

512 MB (internal 128 MB)

4 GB

200 MHz

4 GB

Expanded displacement of LD

and ST instructions

Higher performance

High code efciency

Multiplier

Interrupt responsiveness

Maximum operating frequency

Instructions

Maximum program memory space

Maximum data memory space

5-stage pipeline

Harvard

architecture

2-byte instructions

CISC instructions

16 × 16 bits ⇒ 32 bit

operation

CPU Roadmap

CPU Comparison

PFESiP Roadmap

PFESiP (Platform for Embedded System in a Package) is a new ASIC solution providing Gate Array quickly, cost-effectively, and safely

with expanded functionality, by developing Gate Array and general-purpose function chips into SiPs, which are pre-veried and lined

up as masters.

The EP-3, built around the V850E2M core, is the second in

the EP (Embedded Processor) series of general-function chips

incorporating a microcontroller. The EP-3 combines in a single

package a Renesas 32-bit microcontroller and ASIC chips

such as gate arrays or cell-based ICs. This platform makes it

easy to create customized microcontroller products.

The EP-3 delivers better CPU performance than the EP-1

and operates at a high speed of 266 MHz. It supports high-

speed USB functions and adds new communication interface

functions such as Ethernet and CAN. The optimal bus,

memory, and DMAC conguration helps to eliminate internal

bus bottlenecks.

V850E2M CPU core, max. 266 MHz operation

Programmable logic (requires masking)

Logic capacity: 160,000 to 1 million gates (EA-9HD/CB-12)

Multi-layer system bus

Memory bus: Entirely discrete external bus and SiP internal bus

Internal instruction RAM: Max. 512 KB

Work RAM: 64 KB × 2

Internal DMA controller with descriptor function

Internal serial ash memory controller

USB 2.0 HS ports: Host 1 ch, Function 1 ch

Ethernet: Internal 10/100 EtherMAC

Power supply voltage: Internal 1.0 V, I/O 3.3 V (1.5 V with

CB-12 user logic)

Low-heat-resistance PBGA package

550-pin (25 × 30 mm), 1 mm ball pitch

544-pin (27 × 27 mm), 1 mm ball pitch

Factory automation and industrial equipment

Servers, inverters, PLC equipment, measuring devices,

machine tools, vending machines, security cameras, etc.

Ofce equipment and consumer products

Thermal/dot matrix printers, video/photo printers,

card reader/writers, barcode readers, etc.

PFESiP [EP Series] Roadmap (V850 Core)

EP-3

V850E2M core

266 MHz operation

USB2.0 HS Host/Function

Ether MAC

EP-1

V850E2 core

200 MHz operation

USB2.0 FS Host/Function

EP-2

(In study and planning phase)

V850E2M core

150 MHz operation

USB2.0 HS Host/Function

Low Power

Frequency (MHz)

300

200

100

Ne w

EP-3 overview

EP-3 Features

EP Series applications

EP-3 block diagram

V850E2M CPU SS

INTC

V850E2M

FPU

CPU

MPU

Central DMAC

Custom microcontroller for EP-3

PFESiP/V850EP3

Gate Array, CBIC

User Logic

Bridge

MEMC #2

for SiP

Internal

System

Bus

DMAC

Bus Bridge

16KB m$

wMEM 128KB

USB

2.0 HS

Host

USB

2.0 HS

Function

10/100

Ether

MAC

MEMC #1

for

External

Serial

Flash

MEMC

Serial Flash

ROM

iMEM 512KB

dMEM 32KB

Debug

R/W Buffer

EP-3

External bus

Max. bus width: 32 bits

Max. 100 MHz

SiP internal connection bus

Bus width: 32 bits

Max. 100 MHz

Multi Layer Bus Sub-System

User logic

EA-9HD: 160,000/240,000 gates

CB-12: Up to 1 million gates

PORT

Interval Timer x12ch

Multi Function Timer x8ch

Encoder Timer x2ch

Watchdog Timer

UART with FIFO x4ch

CSI with FIFO x8ch

CAN Controller x2ch

ADC 10bit x8ch

DAC 8bit x2ch (option)

Flash

ROM

SDRAM SRAM I/O

External Bus

This block diagram illustrates the maximum

specications of the EP-3.

The functions that can actually be used by the

microcontroller differ depending on the package.

24 25

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 50 51

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