Renesas M32R-FPU Uživatelský manuál

To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology C

11-2M32R-FPU Software Manual (Rev.1.01)b0b0CPU PROGRAMMING MODEL1.1 CPU Register1.1 CPU RegisterThe M32R family CPU, with a built-in FPU (herein refer

33-62M32R-FPU Software Manual (Rev.1.01)LD24LD24load/store instructionLoad 24-bit immediate[Mnemonic]LD24 Rdest,#imm24[Function]Load the 24-bit immed

33-63 M32R-FPU Software Manual (Rev.1.01)LDBLDBload/store instructionLoad byte[Mnemonic](1) LDB Rdest,@Rsrc(2) LDB Rdest,@(disp16,Rsrc)[Function]L

33-64M32R-FPU Software Manual (Rev.1.01)LDHLDHload/store instructionLoad halfword[Mnemonic](1) LDH Rdest,@Rsrc(2) LDH Rdest,@(disp16,Rsrc)[Functio

33-65 M32R-FPU Software Manual (Rev.1.01)LDILDItransfer instructionLoad immediate[Mnemonic](1) LDI Rdest,#imm8(2) LDI Rdest,#imm16[Function]Load t

33-66M32R-FPU Software Manual (Rev.1.01)LDUBLDUBload/store instructionLoad unsigned byte[Mnemonic](1) LDUB Rdest,@Rsrc(2) LDUB Rdest,@(disp16,Rsrc

33-67 M32R-FPU Software Manual (Rev.1.01)LDUHLDUHload/store instructionLoad unsigned halfword[Mnemonic](1) LDUH Rdest,@Rsrc(2) LDUH Rdest,@(disp16

33-68M32R-FPU Software Manual (Rev.1.01)LOCKLOCKload/store instructionLoad locked[Mnemonic]LOCK Rdest,@Rsrc[Function]Load lockedLOCK = 1, Rdest = *(

33-69 M32R-FPU Software Manual (Rev.1.01)MACHIMACHIDSP function instructionMultiply-accumulate high-order halfwords[Mnemonic]MACHI Rsrc1,Rsrc2[Functi

33-70M32R-FPU Software Manual (Rev.1.01)MACLOMACLODSP function instructionMultiply-accumulate low-order halfwords[Mnemonic]MACLO Rsrc1,Rsrc2[Function

33-71 M32R-FPU Software Manual (Rev.1.01)MACWHIMACWHIDSP function instructionMultiply-accumulateword and high-order halfword[Mnemonic]MACWHI Rsrc1,Rs

11-3 M32R-FPU Software Manual (Rev.1.01)CRnb31b0CPU PROGRAMMING MODEL1.3 Control Registers1.3 Control RegistersThere are 6 control registers which are

33-72M32R-FPU Software Manual (Rev.1.01)MACWLOMACWLODSP function instructionMultiply-accumulateword and low-order halfword[Mnemonic]MACWLO Rsrc1,Rsrc

33-73 M32R-FPU Software Manual (Rev.1.01)MULMULmultiply and divide instructionMultiply[Mnemonic]MUL Rdest,Rsrc[Function]Multiply{ signed64bit tmp;tm

33-74M32R-FPU Software Manual (Rev.1.01)MULHIMULHIDSP function instructionMultiply high-order halfwords[Mnemonic]MULHI Rsrc1,Rsrc2[Function]Multiplya

33-75 M32R-FPU Software Manual (Rev.1.01)MULLOMULLODSP function instructionMultiply low-order halfwords[Mnemonic]MULLO Rsrc1,Rsrc2[Function]Multiplya

33-76M32R-FPU Software Manual (Rev.1.01)MULWHIMULWHIDSP function instructionMultiplyword and high-order halfword[Mnemonic]MULWHI Rsrc1,Rsrc2[Functio

33-77 M32R-FPU Software Manual (Rev.1.01)MULWLOMULWLODSP fucntion instructionMultiplyword and low-order halfword[Mnemonic]MULWLO Rsrc1,Rsrc2[Function

33-78M32R-FPU Software Manual (Rev.1.01)MVMVtransfer instructionMove register[Mnemonic]MV Rdest,Rsrc[Function]TransferRdest = Rsrc;[Description]MV mo

33-79 M32R-FPU Software Manual (Rev.1.01)MVFACHIMVFACHIDSP function instructionMove high-order wordfrom accumulator[Mnemonic]MVFACHI Rdest[Function]T

33-80M32R-FPU Software Manual (Rev.1.01)MVFACLOMVFACLODSP function instructionMove low-order wordfrom accumulator[Mnemonic]MVFACLO Rdest[Function]Tra

33-81 M32R-FPU Software Manual (Rev.1.01)MVFACMIMVFACMIDSP function instructionMove middle-order wordfrom accumulator[Mnemonic]MVFACMI Rdest[Functio

11-4M32R-FPU Software Manual (Rev.1.01)CPU PROGRAMMING MODEL1.3 Control RegistersThe Processor Status Word Register (PSW) indicates the M32R-FPU statu

33-82M32R-FPU Software Manual (Rev.1.01)MVFCMVFCtransfer instructionMove from control register[Mnemonic]MVFC Rdest,CRsrc[Function]Transfer from contr

33-83 M32R-FPU Software Manual (Rev.1.01)MVTACHIMVTACHIDSP function instructionMove high-order wordto accumulator[Mnemonic]MVTACHI Rsrc[Function]Tran

33-84M32R-FPU Software Manual (Rev.1.01)MVTACLOMVTACLODSP function instructionMove low-order wordto accumulator[Mnemonic]MVTACLO Rsrc[Function]Transf

33-85 M32R-FPU Software Manual (Rev.1.01)MVTCMVTCtransfer instructionMove to control register[Mnemonic]MVTC Rsrc,CRdest[Function]Transfer from regist

33-86M32R-FPU Software Manual (Rev.1.01)NEGNEGarithmetic operation instructionNegate[Mnemonic]NEG Rdest,Rsrc[Function]NegateRdest = 0 – Rsrc ;[Descri

33-87 M32R-FPU Software Manual (Rev.1.01)NOPNOPbranch instructionNo operation[Mnemonic]NOP[Function]No operation/* */[Description]NOP performs no op

33-88M32R-FPU Software Manual (Rev.1.01)NOTNOTlogic operation instructionLogical NOT[Mnemonic]NOT Rdest,Rsrc[Function]Logical NOTRdest = ~ Rsrc ;[Des

33-89 M32R-FPU Software Manual (Rev.1.01)ORORlogic operation instructionOR[Mnemonic]OR Rdest,Rsrc[Function]Logical ORRdest = Rdest | Rsrc ;[Descrip

33-90M32R-FPU Software Manual (Rev.1.01)OR3OR3logic operation instructionOR 3-operand[Mnemonic]OR3 Rdest,Rsrc,#imm16[Function]Logical ORRdest = Rsrc

33-91 M32R-FPU Software Manual (Rev.1.01)RACRACDSP function instructionRound accumulator[Mnemonic]RAC[Function]Saturation Process{ signed64bit tmp;tmp

11-5 M32R-FPU Software Manual (Rev.1.01)b0CPU PROGRAMMING MODEL1.3 Control Registers1.3.2 Condition Bit Register: CBR (CR1)The Condition Bit Register

33-92M32R-FPU Software Manual (Rev.1.01)[Supplement]This instruction is executed in two steps as shown below:<step 1><step 2>The value in

33-93 M32R-FPU Software Manual (Rev.1.01)RACHRACHDSP function instructionRound accumulator halfword[Mnemonic]RACH[Function]Saturation Process{ signed6

33-94M32R-FPU Software Manual (Rev.1.01)[Supplement]This instruction is executed in two steps, as shown below.<proccess 1><proccess 2>The

33-95 M32R-FPU Software Manual (Rev.1.01)REMREMmultiply and divide instructionRemainder[Mnemonic]REM Rdest,Rsrc[Function]Signed remainderRdest = ( s

33-96M32R-FPU Software Manual (Rev.1.01)REMUREMUmultiply and divide instructionRemainder unsigned[Mnemonic]REMU Rdest,Rsrc[Function]Unsigned remainde

33-97 M32R-FPU Software Manual (Rev.1.01)RTERTEEIT-related instructionReturn from EIT[Mnemonic]RTE[Function]Return from EITSM = BSM ;IE = BIE ;C = BC

33-98M32R-FPU Software Manual (Rev.1.01)SETHSETHTransfer instructionsSet high-order 16-bit[Mnemonic]SETH Rdest,#imm16[Function]Transfer instructionsR

33-99 M32R-FPU Software Manual (Rev.1.01)INSTRUCTIONS3.2 Instruction descriptionSETPSWSETPSWBit Operation InstructionsSet PSW[M32R-FPU Extended Instru

33-100M32R-FPU Software Manual (Rev.1.01)SLLSLLshift instructionShift left logical[Mnemonic]SLL Rdest,Rsrc[Function]Logical left shiftRdest = Rdest

33-101 M32R-FPU Software Manual (Rev.1.01)SLL3SLL3shift instructionShift left logical 3-operand[Mnemonic]SLL3 Rdest,Rsrc,#imm16[Function]Logical left

11-6M32R-FPU Software Manual (Rev.1.01)CPU PROGRAMMING MODEL1.3 Control Registers<At reset release: H0000 0100>b Bit Name Function R W0 FS Refle

33-102M32R-FPU Software Manual (Rev.1.01)SLLISLLIshift instructionShift left logical immediate[Mnemonic]SLLI Rdest,#imm5[Function]Logical left shiftR

33-103 M32R-FPU Software Manual (Rev.1.01)SRASRAshift instructionShift right arithmetic[Mnemonic]SRA Rdest,Rsrc[Function]Arithmetic right shiftRdest

33-104M32R-FPU Software Manual (Rev.1.01)SRA3SRA3shift instructionShift right arithmetic 3-operand[Mnemonic]SRA3 Rdest,Rsrc,#imm16[Function]Arithmeti

33-105 M32R-FPU Software Manual (Rev.1.01)SRAISRAIshift instructionShift right arithmetic immediate[Mnemonic]SRAI Rdest,#imm5[Function]Arithmetic rig

33-106M32R-FPU Software Manual (Rev.1.01)SRLSRLshift instructionShift right logical[Mnemonic]SRL Rdest,Rsrc[Function]Logical right shiftRdest = ( uns

33-107 M32R-FPU Software Manual (Rev.1.01)SRL3SRL3shift instructionShift right logical 3-operand[Mnemonic]SRL3 Rdest,Rsrc,#imm16[Function]Logical rig

33-108M32R-FPU Software Manual (Rev.1.01)SRLISRLIshift instructionShift right logical immediate[Mnemonic]SRLI Rdest,#imm5[Function]Logical right shif

33-109 M32R-FPU Software Manual (Rev.1.01)STSTload/store instructionStore[Mnemonic](1) ST Rsrc1,@Rsrc2(2) ST Rsrc1,@+Rsrc2(3) ST Rsrc1,@-Rsrc2(4

33-110M32R-FPU Software Manual (Rev.1.01)[Encoding]src11010src100100111 src20100 src2disp16src100100110 src2src100100100 src2ST Rsrc1,@Rsrc2ST Rsrc1

33-111 M32R-FPU Software Manual (Rev.1.01)STBSTBload/store instructionStore byte[Mnemonic](1) STB Rsrc1,@Rsrc2(2) STB Rsrc1,@(disp16,Rsrc2)[Functi

11-7 M32R-FPU Software Manual (Rev.1.01)CPU PROGRAMMING MODEL1.3 Control Registers21 EV 0: Mask EIT processing to be executed when an R WInvalid Opera

33-112M32R-FPU Software Manual (Rev.1.01)STHSTHload/store instructionStore halfword[M32R-FPU Extended Mnemonic][Mnemonic](1) STH Rsrc1,@Rsrc2(2) ST

33-113 M32R-FPU Software Manual (Rev.1.01)SUBSUBarithmetic operation instructionSubtract[Mnemonic]SUB Rdest,Rsrc[Function]SubtractRdest = Rdest - Rsr

33-114M32R-FPU Software Manual (Rev.1.01)SUBVSUBVarithmetic operation instructionSubtract with overflow checking[Mnemonic]SUBV Rdest,Rsrc[Function]Su

33-115 M32R-FPU Software Manual (Rev.1.01)SUBXSUBXarithmetic operation instructionSubtract with borrow[Mnemonic]SUBX Rdest,Rsrc[Function]SubtractRdes

33-116M32R-FPU Software Manual (Rev.1.01)TRAPTRAPEIT-related instructionTrap[Mnemonic]TRAP #imm4[Function]Trap occurrenceBPC = PC + 4;BSM = SM;BIE =

33-117 M32R-FPU Software Manual (Rev.1.01)UNLOCKUNLOCKload/store instructionStore unlocked[Mnemonic]UNLOCK Rsrc1,@Rsrc2[Function]Store unlockedif ( L

33-118M32R-FPU Software Manual (Rev.1.01)INSTRUCTIONS3.2 Instruction descriptionUTOFUTOFFloating Point InstructionsUnsigned integer to float[M32R-FPU

33-119 M32R-FPU Software Manual (Rev.1.01)XORXORlogic operation instructionExclusive OR[Mnemonic]XOR Rdest,Rsrc[Function]Exclusive ORRdest = ( unsign

33-120M32R-FPU Software Manual (Rev.1.01)XOR3XOR3logic operation instructionExclusive OR 3-operand[Mnemonic]XOR3 Rdest,Rsrc,#imm16[Function]Exclusive

APPENDICESAPPENDIX 1 Hexadecimal Instraction CodeAPPENDIX 2 Instruction ListAPPENDIX 3 Pipeline ProcessingAPPENDIX 4 Instruction Execution TimeAPPENDI

11-8M32R-FPU Software Manual (Rev.1.01)CPU PROGRAMMING MODEL1.3 Control Registers1.3.6 Floating-point Exceptions (FPE)Floating-point Exception (FPE) o

APPENDICESAPPENDICES-2M32R-FPU Software Manual (Rev.1.01)Appendix1 Hexadecimal Instraction CodeThe bit pattern of each instruction and correspondence

APPENDICESAPPENDICES-3 M32R-FPU Software Manual (Rev.1.01)1000 1001 1010 1011 11001101 1110111189 BCDEFAb8-b11b0-b3hexadecimalnumeral16-bit instructio

APPENDICESAPPENDICES-4M32R-FPU Software Manual (Rev.1.01)mnemonic function condition bit (C)ADD Rdest,Rsrc Rdest = Rdest + Rsrc –ADD3 Rdest,Rsrc,#imm1

APPENDICESAPPENDICES-5 M32R-FPU Software Manual (Rev.1.01)mnemonic function condition bit (C)FMADD Rdest,Rsrc1,Rsrc2 Rdest = Rdest + Rsrc1 * Rsrc2 –FM

APPENDICESAPPENDICES-6M32R-FPU Software Manual (Rev.1.01)mnemonic function condition bit (C)NEG Rdest,Rsrc Rdest = 0 - Rsrc –NOP /*no-operation*/ –NOT

APPENDICESAPPENDICES-7 M32R-FPU Software Manual (Rev.1.01)where:typedef singed int s; /* 32 bit signed integer (word)*/typedef unsigned int u

APPENDICESAPPENDICES-8M32R-FPU Software Manual (Rev.1.01)Appendix 3 Pipeline ProcessingAppendix 3.1 Instructions and Pipeline ProcessingAppendix Fi

APPENDICESAPPENDICES-9 M32R-FPU Software Manual (Rev.1.01)The overview of each pipeline stage is shown below.● IF stage (instruction fetch stage)The i

APPENDICESAPPENDICES-10M32R-FPU Software Manual (Rev.1.01)Appendix Figure 3.2.1 Pipeline Flow with no Stall (1)Appendix 3.2 Pipeline Basic Operation

APPENDICESAPPENDICES-11 M32R-FPU Software Manual (Rev.1.01)Appendix Figure 3.2.2 Pipeline Flow with no Stall (2)<Case 4> Three FPU instruction

11-9 M32R-FPU Software Manual (Rev.1.01)CPU PROGRAMMING MODEL1.3 Control Registers(3) Inexact Exception (IXCT)The exception occurs when the operation

APPENDICESAPPENDICES-12M32R-FPU Software Manual (Rev.1.01)(2) Pipeline Flow with StallsA pipeline stage may stall due to execution of a process or bra

APPENDICESAPPENDICES-13 M32R-FPU Software Manual (Rev.1.01)Appendix Figure 3.2.4 Pipeline Flow with Stalls (2)<Case 3> A branch instruction is

APPENDICESAPPENDICES-14M32R-FPU Software Manual (Rev.1.01)Appendix Figure 3.2.5 Pipeline Flow with Stalls (3)<Case 6> FPSR is accessed by an MV

APPENDICESAPPENDICES-15 M32R-FPU Software Manual (Rev.1.01)Appendix Figure 3.2.6 Pipeline Flow with Stalls (4)<Case 8> The FPU and integer ins

APPENDICESAPPENDICES-16M32R-FPU Software Manual (Rev.1.01)Appendix Figure 3.2.7 Pipeline Flow with Stalls (5)<Case 12> The FPU and FMADD/FMSUB

APPENDICESAPPENDICES-17 M32R-FPU Software Manual (Rev.1.01)Appendix 4 Instruction Execution TimeNormally, the E stage is considered as representing a

APPENDICESAPPENDICES-18M32R-FPU Software Manual (Rev.1.01)Appendix 5 IEEE754 Specification OverviewThe following is a basic overview of the IEEE754 sp

APPENDICESAPPENDICES-19 M32R-FPU Software Manual (Rev.1.01)APPENDIX 5Appendix 5 IEEE754 Specification OverviewAppendix Table 5.1.1 Single Precision F

APPENDICESAPPENDICES-20M32R-FPU Software Manual (Rev.1.01)APPENDIX 5Appendix 5 IEEE754 Specification OverviewAppendix 5.2 RoundingThe following 4 roun

APPENDICESAPPENDICES-21 M32R-FPU Software Manual (Rev.1.01)(2) Underflow Exception (UDF)The exception occurs when the absolute value of the operation

11-10M32R-FPU Software Manual (Rev.1.01)CPU PROGRAMMING MODEL1.3 Control Registers(5) Invalid Operation Exception (IVLD)The exception occurs when an i

APPENDICESAPPENDICES-22M32R-FPU Software Manual (Rev.1.01)APPENDIX 5Appendix 5 IEEE754 Specification Overview(5) Invalid Operation Exception (IVLD)The

APPENDICESAPPENDICES-23 M32R-FPU Software Manual (Rev.1.01)Appendix 6 M32R-FPU Specification Supplemental ExplanationAppendix 6.1 Operation Comparisio

APPENDICESAPPENDICES-24M32R-FPU Software Manual (Rev.1.01)(1) Overflow occurs in Step 1<When EO = 0, EX = 0: OVF and IXCT occur>Type of R0 Condi

APPENDICESAPPENDICES-25 M32R-FPU Software Manual (Rev.1.01)(2) When underflow occurs in Step 1<When EU = 0, DN = 1: UDF occurs>Type of R0 Condit

APPENDICESAPPENDICES-26M32R-FPU Software Manual (Rev.1.01)APPENDIX 6Appendix 6 M32R-FPU Specification Supplemental Explanation(3) When Invalid Operati

APPENDICESAPPENDICES-27 M32R-FPU Software Manual (Rev.1.01)(4) When Inexact Operation Exception occurs in Step 1 If an Inexact Operation occurs due t

APPENDICESAPPENDICES-28M32R-FPU Software Manual (Rev.1.01)APPENDIX 6Appendix 6 M32R-FPU Specification Supplemental ExplanationAppendix 6.2 Rules conce

APPENDICESAPPENDICES-29 M32R-FPU Software Manual (Rev.1.01)Appendix 7 PrecautionsAppendix 7.1 Precautions to be taken when aligning dataWhen aligning

APPENDICESAPPENDICES-30M32R-FPU Software Manual (Rev.1.01)This page left blank intentionally.APPENDIX 7Appendix 7 Precautions

INDEX

11-11 M32R-FPU Software Manual (Rev.1.01)CPU PROGRAMMING MODEL1.4 Accumulator1.4 AccumulatorThe Accumulator (ACC) is a 56-bit register used for DSP fu

INDEXINDEX-2M32R-FPU Software Manual (Rev.1.01)Symbol#imm 1-15, 3-2@(disp,R) 1-15, 3-2@+R 1-15, 3-2@-R 1-15, 3-2@R 1-15, 3-2@R+ 1-15, 3-2AAccumulator(

INDEXINDEX-3 M32R-FPU Software Manual (Rev.1.01)LLoad/store instructions 2-2LD 3-61LDB 3-63LDH 3-64LDUB 3-66LDUH 3-67LOCK 3-68ST 3-109STB 3-111STH 3-1

INDEXINDEX-4M32R-FPU Software Manual (Rev.1.01)RR 1-15, 3-2Register direct(R or CR) 1-15, 3-2Register indirect(@R) 1-15, 3-2Register indirect and regi

RENESAS 32-BIT RISC SINGLE-CHIP MICROCOMPUTERSOFTWARE MANUALM32R-FPUPublication Data : Rev.1.00 Jan 08, 2003Rev.1.01 Oct 31, 2003Published by : Sale

1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 JapanM32R-FPUREJ09B0112-0101ZSoftware Manual

Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to chang

11-12M32R-FPU Software Manual (Rev.1.01)1.6 Data Format1.6.1 Data TypeThe data types that can be handled by the M32R-FPU instruction set are signed or

11-13 M32R-FPU Software Manual (Rev.1.01)1.6.2 Data Format(1) Data format in a registerThe data sizes in the M32R-FPU registers are always words (32 b

11-14M32R-FPU Software Manual (Rev.1.01)(2) Data format in memoryThe data sizes in memory can be byte (8 bits), halfword (16 bits) or word (32 bits).A

11-15 M32R-FPU Software Manual (Rev.1.01)1.7 Addressing ModeM32R-FPU supports the following addressing modes.(1) Register direct [R or CR]The general-

11-16M32R-FPU Software Manual (Rev.1.01)CPU PROGRAMMING MODEL1.7 Addressing ModeThis page left blank intentionally.

CHAPTER 2INSTRUCTION SET2.1 Instruction set overview2.2 Instruction format

22-2M32R-FPU Software Manual (Rev.1.01)2.1 Instruction set overviewThe M32R-FPU has a total of 100 instructions. The M32R-FPU has a RISC architecture.

22-3 M32R-FPU Software Manual (Rev.1.01)INSTRUCTION SET2.1 Instruction set overviewThree types of addressing modes can be specified for load/store ins

22-4M32R-FPU Software Manual (Rev.1.01)2.1.2 Transfer instructionsThe transfer instructions carry out data transfers between registers or a register a

22-5 M32R-FPU Software Manual (Rev.1.01)• logic operation instructionsAND ANDAND3 AND 3-operandNOT Logical NOTOR OROR3 OR 3-operandXOR Exclusive ORXOR

M32R-FPUSoftware Manual32Rev.1.01 2003.10RENESAS 32-BIT RISC SINGLE-CHIP MICROCOMPUTERAll information contained in these materials, including produc

22-6M32R-FPU Software Manual (Rev.1.01)2.1.4 Branch instructionsThe branch instructions are used to change the program flow.BC Branch on C-bitBEQ Bran

22-7 M32R-FPU Software Manual (Rev.1.01)The addressing mode of the BRA, BL, BC and BNC instructions can specify an 8-bit or24-bit immediate value. The

22-8M32R-FPU Software Manual (Rev.1.01)2.1.5 EIT-related instructionsThe EIT-related instructions carry out the EIT events (Exception, Interrupt and T

22-9 M32R-FPU Software Manual (Rev.1.01)Fig. 2.1.2 DSP function instruction operation 1 (multiply, multiply and accumulate)Rsrc10151631HACC063L0151631

22-10M32R-FPU Software Manual (Rev.1.01)ACC063sign 0RAC instructionACC063sign 0RACH instruction< word size round off > < halfword size round

22-11 M32R-FPU Software Manual (Rev.1.01)INSTRUCTION SET2.1 Instruction set overview2.1.7 Floating-point InstructionsThe following instructions execut

22-12M32R-FPU Software Manual (Rev.1.01)2.2 Instruction formatThere are two major instruction formats: two 16-bit instructions packed together within

22-13 M32R-FPU Software Manual (Rev.1.01)The MSB (Most Significant Bit) of a 32-bit instruction is always "1". The MSB of a 16-bitinstructio

22-14M32R-FPU Software Manual (Rev.1.01)This page left blank intentionally.INSTRUCTION SET2.2 Instruction format

CHAPTER 3INSTRUCTIONS3.1 Conventions for instructiondescription3.2 Instruction description

Keep safety first in your circuit designs!Notes regarding these materials•Renesas Technology Corporation puts the maximum effort into making semicondu

33-2M32R-FPU Software Manual (Rev.1.01)3.1 Conventions for instruction descriptionConventions for instruction description are summarized below.[Mnemon

33-3 M32R-FPU Software Manual (Rev.1.01)Table 3.1.3 Operation expression (operator) (cont.)operator meaning- sign invert (monomial operator)= substitu

33-4M32R-FPU Software Manual (Rev.1.01)[Description]Describes the operation performed by the instruction and any condition bit change.[EIT occurrence]

33-5 M32R-FPU Software Manual (Rev.1.01)3.2 Instruction descriptionThis section lists M32R-FPU instructions in alphabetical order. Each page is laid o

33-6M32R-FPU Software Manual (Rev.1.01)ADDdest0000 ADD Rdest,RsrcADD1010arithmetic/logic operationAddsrc[Mnemonic]ADD Rdest,Rsrc[Function]AddRdest =

33-7 M32R-FPU Software Manual (Rev.1.01)ADD3[Mnemonic]ADD3 Rdest,Rsrc,#imm16[Function]AddRdest = Rsrc + ( signed short ) imm16;[Description]ADD3 adds

33-8M32R-FPU Software Manual (Rev.1.01)ADDI[Mnemonic]ADDI Rdest,#imm8[Function]Add Rdest = Rdest + ( signed char ) imm8;[Description]ADDI adds the 8-

33-9 M32R-FPU Software Manual (Rev.1.01)ADDV[Mnemonic]ADDV Rdest,Rsrc[Function]AddRdest = ( signed ) Rdest + ( signed ) Rsrc;C = overflow ? 1 : 0;

33-10M32R-FPU Software Manual (Rev.1.01)ADDV3[Mnemonic]ADDV3 Rdest,Rsrc,#imm16[Function]AddRdest = ( signed ) Rsrc + ( signed ) ( ( signed short ) im

33-11 M32R-FPU Software Manual (Rev.1.01)ADDX[Mnemonic]ADDX Rdest,Rsrc[Function]AddRdest = ( unsigned ) Rdest + ( unsigned ) Rsrc + C;C = carry_out

REVISION HISTORYRev. Date DescriptionPage SummaryM32R-FPU Software Manual1.00 Jan 08, 2003 First edition issued –1.01 Oct 31, 2003 Hexadecimal Ins

33-12M32R-FPU Software Manual (Rev.1.01)ANDAND11000000 AND Rdest,Rsrclogic operation instructionANDsrcdest[Mnemonic]AND Rdest,Rsrc[Function]Logical A

33-13 M32R-FPU Software Manual (Rev.1.01)AND3[Mnemonic]AND3 Rdest,Rsrc,#imm16[Function]Logical ANDRdest = Rsrc & ( unsigned short ) imm16;[Descri

33-14M32R-FPU Software Manual (Rev.1.01)BCBC[Mnemonic](1) BC pcdisp8(2) BC pcdisp24[Function]Branch(1) if ( C==1 ) PC = ( PC & 0xfffffffc )

33-15 M32R-FPU Software Manual (Rev.1.01)bit operationBit clear[M32R-FPU Extended Instruction]INSTRUCTIONS3.2 Instruction descriptionBCLRBCLR[Mnemonic

33-16M32R-FPU Software Manual (Rev.1.01)BEQBEQbranch instructionBranch on equal to[Mnemonic]BEQ Rsrc1,Rsrc2,pcdisp16[Function]Branchif ( Rsrc1 == Rsr

33-17 M32R-FPU Software Manual (Rev.1.01)BEQZBEQZbranch instructionBranch on equal to zero[Mnemonic]BEQZ Rsrc,pcdisp16[Function]Branchif ( Rsrc == 0

33-18M32R-FPU Software Manual (Rev.1.01)BGEZBGEZbranch instructionBranch on greater than or equal to zero[Mnemonic]BGEZ Rsrc,pcdisp16[Function]Branch

33-19 M32R-FPU Software Manual (Rev.1.01)BGTZBGTZbranch instructionBranch on greater than zero[Mnemonic]BGTZ Rsrc,pcdisp16[Function]Branchif ((signed

33-20M32R-FPU Software Manual (Rev.1.01)BLBLbranch instructionBranch and link[Mnemonic](1) BL pcdisp8(2) BL pcdisp24[Function]Subroutine call (PC

33-21 M32R-FPU Software Manual (Rev.1.01)BLEZBLEZbranch instructionBranch on less than or equal to zero[Mnemonic]BLEZ Rsrc,pcdisp16[Function]Branchif

M32R-FPU Software Manual (Rev.1.01)(1)Table of contentsCHAPTER 1 CPU PROGRAMMING MODEL1.1 CPU register ...

33-22M32R-FPU Software Manual (Rev.1.01)BLTZBLTZbranch instructionBranch on less than zero[Mnemonic]BLTZ Rsrc,pcdisp16[Function]Branchif ((signed) Rs

33-23 M32R-FPU Software Manual (Rev.1.01)BNCBNCbranch instructionBranch on not C-bit[Mnemonic](1) BNC pcdisp8(2) BNC pcdisp24[Function]Branch(1)

33-24M32R-FPU Software Manual (Rev.1.01)BNEBNEbranch instructionBranch on not equal to[Mnemonic]BNE Rsrc1,Rsrc2,pcdisp16[Function]Branchif ( Rsrc1 !=

33-25 M32R-FPU Software Manual (Rev.1.01)BNEZBNEZbranch instructionBranch on not equal to zero[Mnemonic]BNEZ Rsrc,pcdisp16[Function]Branchif ( Rsrc !

33-26M32R-FPU Software Manual (Rev.1.01)BRABRAbranch instructionBranch[Mnemonic](1) BRA pcdisp8(2) BRA pcdisp24[Function]Branch(1) PC = ( PC &

33-27 M32R-FPU Software Manual (Rev.1.01)BSETBSETINSTRUCTIONS3.2 Instruction descriptionbit operation InstructionsBit set[M32R-FPU Extended Instructio

33-28M32R-FPU Software Manual (Rev.1.01)BTSTBTSTINSTRUCTIONS3.2 Instruction descriptionbit operation InstructionsBit test[M32R-FPU Extended Instructio

33-29 M32R-FPU Software Manual (Rev.1.01)CLRPSWCLRPSWINSTRUCTIONS3.2 Instruction descriptionbit operation InstructionsClear PSW[M32R-FPU Extended Inst

33-30M32R-FPU Software Manual (Rev.1.01)CMP[Mnemonic]CMP Rsrc1,Rsrc2[Function]CompareC = ( ( signed ) Rsrc1 < ( signed ) Rsrc2 ) ? 1:0;[Descri

33-31 M32R-FPU Software Manual (Rev.1.01)CMPI[Mnemonic]CMPI Rsrc,#imm16[Function]CompareC = ( ( signed ) Rsrc < ( signed short ) imm16 ) ? 1:0

M32R-FPU Software Manual (Rev.1.01)CHAPTER 3 INSTRUCTIONS3.1 Conventions for instruction description ...

33-32M32R-FPU Software Manual (Rev.1.01)CMPU[Mnemonic]CMPU Rsrc1,Rsrc2[Function]CompareC = ( ( unsigned ) Rsrc1 < ( unsigned ) Rsrc2 ) ? 1:0;[

33-33 M32R-FPU Software Manual (Rev.1.01)CMPUI[Mnemonic]CMPUI Rsrc,#imm16[Function]CompareC = ( ( unsigned ) Rsrc < ( unsigned ) ( ( signed shor

33-34M32R-FPU Software Manual (Rev.1.01)dest1001 src0000 00000000 00000000DIV Rdest,RsrcDIV[Mnemonic]DIV Rdest,Rsrc[Function]Signed divisionRdest =

33-35 M32R-FPU Software Manual (Rev.1.01)DIVU[Mnemonic]DIVU Rdest,Rsrc[Function]Unsigned divisionRdest = ( unsigned ) Rdest / ( unsigned ) Rsrc;[De

33-36M32R-FPU Software Manual (Rev.1.01)INSTRUCTIONS3.2 Instruction descriptionFADDFADD[Mnemonic]FADD Rdest,Rsrc1,Rsrc2[Function]Floating-point addRd

33-37 M32R-FPU Software Manual (Rev.1.01)INSTRUCTIONS3.2 Instruction description[Supplemental Operation Description]The following shows the values of

33-38M32R-FPU Software Manual (Rev.1.01)INSTRUCTIONS3.2 Instruction descriptionFCMPFCMPsrc11101 src20000 dest0000 00001100FCMP Rdest,Rsrc1,Rsrc2[Mnem

33-39 M32R-FPU Software Manual (Rev.1.01)INSTRUCTIONS3.2 Instruction description[Supplemental Operation Description]The following shows the values of

33-40M32R-FPU Software Manual (Rev.1.01)INSTRUCTIONS3.2 Instruction descriptionFCMPEFCMPEsrc11101 src20000 dest0000 00001101FCMPE Rdest,Rsrc1,Rsrc2[M

33-41 M32R-FPU Software Manual (Rev.1.01)INSTRUCTIONS3.2 Instruction description[Supplemental Operation Description]The following shows the values of

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33-42M32R-FPU Software Manual (Rev.1.01)INSTRUCTIONS3.2 Instruction descriptionFDIVFDIV[Mnemonic]FDIV Rdest,Rsrc1,Rsrc2[Function]Floating-point divid

33-43 M32R-FPU Software Manual (Rev.1.01)INSTRUCTIONS3.2 Instruction description[Supplemental Operation Description]The following shows the values of

33-44M32R-FPU Software Manual (Rev.1.01)INSTRUCTIONS3.2 Instruction descriptionFMADDFMADD[Mnemonic]FMADD Rdest,Rsrc1,Rsrc2[Function]Floating-point mu

33-45 M32R-FPU Software Manual (Rev.1.01)INSTRUCTIONS3.2 Instruction description[Supplemental Operation Description]The following shows the values of

33-46M32R-FPU Software Manual (Rev.1.01)INSTRUCTIONS3.2 Instruction descriptionDN=1Value after Multiplication OperationValue after Addition OperationI

33-47 M32R-FPU Software Manual (Rev.1.01)INSTRUCTIONS3.2 Instruction descriptionFMSUBFMSUB[Mnemonic]FMSUB Rdest,Rsrc1,Rsrc2[Function]Floating-point m

33-48M32R-FPU Software Manual (Rev.1.01)INSTRUCTIONS3.2 Instruction description[Supplemental Operation Description]The following shows the values of R

33-49 M32R-FPU Software Manual (Rev.1.01)INSTRUCTIONS3.2 Instruction descriptionDN=1Value after Multiplication OperationValue after Subtraction Operat

33-50M32R-FPU Software Manual (Rev.1.01)INSTRUCTIONS3.2 Instruction descriptionFMULFMUL[Mnemonic]FMUL Rdest,Rsrc1,Rsrc2[Function]Floating-point multi

33-51 M32R-FPU Software Manual (Rev.1.01)INSTRUCTIONS3.2 Instruction description[Supplemental Operation Description]The following shows the values of

CHAPTER 1CPU PROGRAMMIING MODEL1.1 CPU Register1.2 General-purpose Registers1.3 Control Registers1.4 Accumulator1.5 Program Counter1.6 Data Format1.7

33-52M32R-FPU Software Manual (Rev.1.01)INSTRUCTIONS3.2 Instruction descriptionFSUBFSUB[Mnemonic]FSUB Rdest,Rsrc1,Rsrc2[Function]Floating-point subtr

33-53 M32R-FPU Software Manual (Rev.1.01)INSTRUCTIONS3.2 Instruction descriptionRsrc2SubtractionUIPLQNaNQNaNSNaNQNaNSNaN+0+0+0(Note)(Note)+Infinity+In

33-54M32R-FPU Software Manual (Rev.1.01)INSTRUCTIONS3.2 Instruction descriptionFTOIFTOI[Mnemonic]FTOI Rdest,Rsrc[Function]Convert the floating-point

33-55 M32R-FPU Software Manual (Rev.1.01)[Supplemental Operation Description]The results of the FTOI instruction executed based on the Rsrc value, bot

33-56M32R-FPU Software Manual (Rev.1.01)INSTRUCTIONS3.2 Instruction descriptionFTOSFTOS[Mnemonic]FTOS Rdest,Rsrc[Function]Convert the floating-point

33-57 M32R-FPU Software Manual (Rev.1.01)INSTRUCTIONS3.2 Instruction description[Supplemental Operation Description]The results of the FTOS instructio

33-58M32R-FPU Software Manual (Rev.1.01)INSTRUCTIONS3.2 Instruction descriptionITOFITOF[Mnemonic]ITOF Rdest,Rsrc[Function]Convert the integer to a fl

33-59 M32R-FPU Software Manual (Rev.1.01)JLJLbranch instructionJump and link[Mnemonic]JL Rsrc[Function]Subroutine call (register direct)R14 = ( PC &a

33-60M32R-FPU Software Manual (Rev.1.01)JMPJMPbranch instructionJump[Mnemonic]JMP Rsrc[Function]JumpPC = Rsrc & 0xfffffffc;[Description]JMP caus

33-61 M32R-FPU Software Manual (Rev.1.01)LDLDload/store instructionLoad[Mnemonic](1) LD Rdest,@Rsrc(2) LD Rdest,@Rsrc+(3) LD Rdest,@(disp16,Rsrc