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1
1-11 M32R-FPU Software Manual (Rev.1.01)
CPU PROGRAMMING MODEL
1.4 Accumulator
1.4 Accumulator
The Accumulator (ACC) is a 56-bit register used for DSP function instructions.
The accumulator is handled as a 64-bit register when accessed for read or write.
When reading data from the accumulator, the value of bit 8 is sign-extended. When
writing data to the accumulator, bits 0 to 7 are ignored. The accumulator is also used
for the multiply instruction "MUL", in which case the accumulator value is destroyed
by instruction execution.
Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The
MVTACHI and MVTACLO instructions write data to the high-order 32 bits (bits 0-31)
and the low-order 32 bits (bits 32-63), respectively.
Use the MVFACHI, MVFACLO, and MVFACMI instructions for reading data from the
accumulator. The MVFACHI, MVFACLO and MVFACMI instructions read data from
the high-order 32 bits (bits 0-31), the low-order 32 bits (bits 32-63) and the middle 32
bits (bits 16-47), respectively.
At reset release, the value of accumulator is undefined.
32 48 b63311615b0 4778
ACC
(Note 1)
read/write range with
MVTACLO or MVFACLO instruction
read/write range with
MVTACHI or MVFACHI instruction
read range with MVFACMI instruction
1.5 Program Counter
The Program Counter (PC) is a 32-bit counter that retains the address of the
instruction being executed. Since the M32R CPU instruction starts with even-
numbered addresses, the LSB (bit 31) is always "0".
At reset release, the value of the PC is "H’0000 0000."
PC
PC
0
b31
b0
Note 1: When read, bits 0 to 7 always show the sign-extended value of bit 8. Writing to this bit field is
ignored.
- To our customers 1
- REVISION HISTORY 5
- M32R-FPU Software Manual 5
- Table of contents 6
- CHAPTER 3 INSTRUCTIONS 7
- APPENDIX 7
- CHAPTER 1 9
- CPU PROGRAMMIING MODEL 9
- 1.1 CPU Register 10
- 1.2 General-purpose Registers 10
- 1.3 Control Registers 11
- CPU PROGRAMMING MODEL 12
- 1.4 Accumulator 19
- 1.5 Program Counter 19
- 1.6 Data Format 20
- 1.7 Addressing Mode 23
- CHAPTER 2 25
- INSTRUCTION SET 25
- 2.1 Instruction set overview 26
- 2.2 Instruction format 36
- CHAPTER 3 39
- 3.2 Instruction description 43
- Add 3-operand 45
- Add immediate 46
- Add with overflow checking 47
- Add with carry 49
- AND 3-operand 51
- Bit clear 52
- M32R-FPU Extended Instruction 52
- BCLRBCLR 53
- Branch on equal to 54
- BEQZBEQZ 55
- BGEZBGEZ 56
- BGTZBGTZ 57
- Branch and link 58
- BLEZBLEZ 59
- BLTZBLTZ 60
- Branch on not C-bit 61
- Branch on not equal to 62
- BNEZBNEZ 63
- BSETBSET 65
- BTSTBTST 66
- CLRPSWCLRPSW 67
- Compare immediate 69
- Compare unsigned 70
- Compare unsigned immediate 71
- Divide unsigned 73
- FADDFADD 74
- FCMPFCMP 76
- FCMPEFCMPE 78
- FDIVFDIV 80
- FMADDFMADD 82
- FMSUBFMSUB 85
- FMULFMUL 88
- FSUBFSUB 90
- FTOIFTOI 92
- FTOSFTOS 94
- ITOFITOF 96
- Jump and link 97
- LD24LD24 100
- Load byte 101
- INSTRUCTIONS 101
- Load halfword 102
- Load immediate 103
- LDUBLDUB 104
- LDUHLDUH 105
- LOCKLOCK 106
- MACHIMACHI 107
- MACLOMACLO 108
- MACWHIMACWHI 109
- MACWLOMACWLO 110
- Multiply 111
- MULHIMULHI 112
- MULLOMULLO 113
- MULWHIMULWHI 114
- MULWLOMULWLO 115
- Move register 116
- MVFACHIMVFACHI 117
- MVFACLOMVFACLO 118
- MVFACMIMVFACMI 119
- MVFCMVFC 120
- MVTACHIMVTACHI 121
- MVTACLOMVTACLO 122
- MVTCMVTC 123
- No operation 125
- Logical NOT 126
- OR 3-operand 128
- Round accumulator 129
- RACHRACH 131
- Remainder 133
- REMUREMU 134
- Return from EIT 135
- SETHSETH 136
- SETPSWSETPSW 137
- Shift left logical 138
- SLL3SLL3 139
- SLLISLLI 140
- Shift right arithmetic 141
- SRA3SRA3 142
- SRAISRAI 143
- Shift right logical 144
- SRL3SRL3 145
- SRLISRLI 146
- Store byte 149
- Store halfword 150
- [M32R-FPU Extended Mnemonic] 150
- Subtract 151
- SUBVSUBV 152
- SUBXSUBX 153
- TRAPTRAP 154
- UNLOCKUNLOCK 155
- UTOFUTOF 156
- Exclusive OR 157
- XOR3XOR3 158
- APPENDICES 159
- M32R-FPU 194
- REJ09B0112-0101Z 194
- Software Manual 194
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