Renesas H8S/2111B Uživatelský manuál stáhnout pdf (Strana 206)

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Rev. 1.00, 05/04, page 172 of 544

9.5.4 Input Capture Input Timing

The rising or falling edge can be selected for the input capture input timing by the IEDGA to

IEDGD bits in TCR. Figure 9.7 shows the usual input capture timing when the rising edge is

selected.

Input capture

input pin

Input capture signal

Figure 9.7 Input Capture Input Signal Timing (Usual Case)

If ICRA to ICRAD are read when the corresponding input capture signal arrives, the internal input

capture signal is delayed by one system clock (φ). Figure 9.8 shows the timing for this case.

Read cycle of ICRA to ICRD

Input capture

input pin

Input capture signal

Figure 9.8 Input Capture Input Signal Timing (When ICRA to ICRD are Read)

1 2 ... 201 202 203 204 205 206 207 208 209 210 211 ... 581 582

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