Renesas R8C/15 Technické informace stáhnout pdf (Strana 144)

R8C/14 Group, R8C/15 Group 14. Serial Interface

Rev.2.10 Jan 19, 2006 Page 130 of 253

REJ09B0164-0210

14.1 Clock Synchronous Serial I/O Mode

The clock synchronous serial I/O mode is mode to transmit and receive data using a transfer clock.

Table 14.1 lists the Specification of Clock Synchronous Serial I/O Mode. Table 14.2 lists the Registers to

Be Used and Settings in Clock Synchronous Serial I/O Mode(1).

NOTES:

1. When an external clock is selected, meet the conditions while the CKPOL bit in the U0C0 register is

set to “0” (transmit data output at the falling edge and the receive data input at the rising edge of the

transfer clock), the external clock is held “H”; if the CKPOL bit in the U0C0 register is set to “1”

(transmit data output at the rising edge and the receive data input at the falling edge of the transfer

clock), the external clock is held “L”.

2. If an overrun error occurs, the value of the U0RB register will be indeterminate. The IR bit in the

S0RIC register remains unchanged.

Table 14.1 Specification of Clock Synchronous Serial I/O Mode

Item Specification

Transfer Data Format • Transfer data length: 8 bits

Transfer Clock •CKDIR bit in U0MR register is set to “0” (internal clock): fi/(2(n+1))

fi=f1, f8, f32 n=setting value in U0BRG register: 00h to FFh

• The CKDIR bit is set to “1” (external clock): input from CLK0 pin

Transmit Start Condition

• Before transmit starts, the following requirements are required

(1)

- The TE bit in the U0C1 register is set to “1” (transmit enabled)

- The TI bit in the U0C1 register is set to “0” (data in the U0TB register)

Receive Start Condition

• Before receive starts, the following requirements are required

(1)

- The RE bit in the U0C1 register is set to “1” (receive enabled)

- The TE bit in the U0C1 register is set to “1” (transmit enabled)

- The TI bit in the U0C1 register is set to “0” (data in the U0TB register)

Interrupt Request

Generation Timing

• When transmit, one of the following conditions can be selected

- The U0IRS bit is set to “0” (transmit buffer empty):

when transferring data from the U0TB register to UART0 transmit register

(when transmit starts)

- The U0IRS bit is set to “1” (transmit completes):

when completing transmit data from UARTi transmit register

• When receive

When transferring data from the UART0 receive register to the U0RB

Error Detection

• Overrun error

(2)

This error occurs if serial interface starts receiving the following data before

reading the U0RB register and receives the 7th bit of the following data

Select Function • CLK polarity selection

Transfer data input/output can be selected to occur synchronously with the

rising or the falling edge of the transfer clock

• LSB first, MSB first selection

Whether transmitting or receiving data beginning with the bit 0 or beginning

with the bit 7 can be selected

• Continuous receive mode selection

Receive is enabled immediately by reading the U0RB register

1 2 ... 139 140 141 142 143 144 145 146 147 148 149 ... 278 279

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