Renesas Single-Chip Microcomputer M38C89T-ADF Uživatelský manuál stáhnout pdf (Strana 121)

4BUsage Examples

5.3 23BBus Controller

5-5

Rev.1.00 May 22 2012

REJ09B0566

Figure 5-2 Example of I/O Port Operations

5.3. Bus Controller

Figure 5-3 shows an example of external bus controller usage.

/* PDL functions */

#include "r_pdl_bsc_library_SH7267.h"

#include "r_pdl_pfc_library_SH7267.h"

#include "r_pdl_cpg_library_SH7267.h"

#include "r_pdl_io_port_library_SH7267.h"

/* PDL device-specific definitions */

#include "r_pdl_definitions.h"

void BSC_error_handler(void);

void BSC_Test(void)

{

uint16_t cs0_location_16_value;

uint16_t * cs0_location_16;

uint16_t * cs3_location_16;

uint8_t status;

cs0_location_16 = ( uint16_t *)0x00000000ul;

cs3_location_16 = (uint16_t *)0x0C000500ul;

/* Setup the LED1 */

R_PFC_Modify(PDL_PJCR1, PDL_PFC_AND, 0xF0FF);

R_IO_PORT_Set(PDL_IO_PORT_J_6, PDL_IO_PORT_OUTPUT, 0);

/* turn off the LED */

_check_Wr_Pin_H(PDL_IO_PORT_J_6,PDL_IO_PORT_LOW);

/* Configure the CS0 Space for NORMAL module. 16 bit bus width, Big Endian, and delay and wait

timings */

R_BSC_CreateAreaAll(PDL_BSC_TYPE_NORMAL,0,0,

PDL_BSC_WIDTH_16|PDL_BSC_BIG_ENDIAN|PDL_BSC_IWW,

PDL_BSC_BAS_DISABLE|PDL_BSC_SW|PDL_BSC_WR|PDL_BSC_HW| \

PDL_BSC_WAIT_ENABLE,

1,6,1,0,0,0,0,0,0,0,0,0,0,0,0,

1,0,0,0,0,0

);

/* create a space with SDRAM control register and SDRAM refresh rate control */

R_BSC_CreateAll(0,0,0,

PDL_BSC_REFERSH_INT_ENABLE |PDL_BSC_REFRESH_DIV_4_CLOCK \

PDL_BSC_REFRESH_COUNTER |PDL_BSC_REFRESH_1_TIME,

0xa55a0046ul,

BSC_error_handler,

);

/* create a CS3 space for SDRAM memory with delay, idle and wait cycles timing */

R_BSC_CreateAreaAll(PDL_BSC_TYPE_SDRAM,3,

PDL_BSC_A3ROW_13|PDL_BSC_A3COL_10|PDL_BSC_RFSH_ENABLE,

PDL_BSC_WIDTH_16|PDL_BSC_BIG_ENDIAN,

PDL_BSC_WTRP|PDL_BSC_WTRCD|PDL_BSC_A3CL|PDL_BSC_TRWL|PDL_BSC_WTRC,

0,0,0,0,0,0,0,

1,2,1,1,2,0,0,0,

0,0,0,0,0,0

);

/* Modify the MCU clocks */

1 2 ... 116 117 118 119 120 121 122 123 124 125 126 ... 137 138

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