Renesas Single-Chip Microcomputer M38C89T-ADF Uživatelský manuál stáhnout pdf (Strana 72)

Rev.1.00 May 22 2012

REJ09B0566

4-52

3BLibrary Reference

R_BSC_CreateArea

4.2.5 36BBus State Controller

Select the parameter that needs to be configured for the WCR register.

• Wait Cycles configuration

PDL_BSC_SW configure sw cycles

PDL_BSC_WR configure wr cycles

PDL_BSC_HW configure hw cycles

PDL_BSC_WW configure ww cycles

PDL_BSC_A2CL configure a2cl cycles

PDL_BSC_WTRP configure wtrp cycles

PDL_BSC_WTRCD configure wtrcd cycles

PDL_BSC_A3CL configure a3cl cycles

PDL_BSC_TRWL configure trwl cycles

PDL_BSC_WTRC configure wtrc cycles

PDL_BSC_TED configure ted cycles

PDL_BSC_PCW configure pcw cycles

PDL_BSC_TEH configure teh cycles

• Write Mode Enable

PDL_BSC_WAIT_DISABLE or

PDL_BSC_WAIT_ENABLE Enable or Disable Write Mode

• Bus With Specification

PDL_BSC_SZSEL_A14 or

PDL_BSC_SZSEL_A15 Set the BUS Width Specification to either 14 or 15 bits

• Burst Count Specification

PDL_BSC_BST_16X1 or

PDL_BSC_BST_4X4

PDL_BSC_BST_8X1 or

PDL_BSC_BST_2x4 or

PDL_BSC_BST_242

Set Burst count specification to either 16x1 type or

4x4 type if bus width is 168 bits

Set Burst count specification to either 8x1 type or

22*4 or 2-4-2 type if bus width is 8 bits

• Space attribute Specification

PDL_BSC_SA1_MEM or

PDL_BSC_SA1_IO Select the space attribute specification for A25=1

PDL_BSC_SA0_MEM or

PDL_BSC_SA0_IO Select the space attribute specification for A25=0

[data6]

The Number of Delay Cycles from Address, CS0 Assertion to RD, WEn Assertionn (SW). Valid between 0

and 3.

[data7]

The number of cycles that are necessary for read/write access (WR). Valid between 0 and 12.

[data8]

The number of delay cycles from RD and WEn negation to address and CS0 negation (HW). Valid between

0 and 3.

[data9]

The number of wait cycles to be inserted between the second or subsequent access cycles in burst access

(BW). Valid between 0 and 3.

[data10]

The number of wait cycles to be inserted in the first access cycle (W). Valid between 0 and 12.

[data11]

The number of cycles that are necessary for write access (WW). Valid between 0 and 6.

[data12]

Specify the CAS latency for area 2 (A2CL). Valid between 0 and 3.

[data13]

The number of minimum precharge completion wait cycles (WTRP). Valid between 0 and 3.

1 2 ... 67 68 69 70 71 72 73 74 75 76 77 ... 137 138

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