
Rev.1.00 May 22 2012
REJ09B0566
Program example
/* PDL definitions */
#include “r_pdl_cpg.h”
/* PDL device-specific definitions */
#include “r_pdl_definitions.h”
void func(void)
{
/* Configure operation using a 18 MHz input clock */
/* ICLK = 144 MHz, PCLK = 36 MHz, BCLK = 72 MHz */
R_CPG_Set (18E6, 144E6, 36E6, PDL_CPG_CK_2, PDL_CPG_OUT_CK_01);
}
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