Renesas User System Interface Board HS7047ECH61H Uživatelský manuál stáhnout pdf (Strana 72)

3.5.2 Low Power-Consumption Mode (Sleep, Software Standby, and Hardware Standby)

For reduced power consumption, the MCU has sleep, software standby, and hardware standby modes.

Hardware Standby Mode

Since the _HSTBY signal from the user system is not input to the MCU in the emulator, the emulator does not

support this mode.

Sleep and Software Standby Modes

• Break

The sleep and software standby modes can be cleared with either the normal clearing function or with the

break condition satisfaction (forced break), and the program breaks. When restarting after a break, the user

program will restart at the instruction following the SLEEP instruction.

• Trace

Trace information is not acquired in these modes.

• Memory access with emulator functions

For information on displaying and modifying the contents of memory in the sleep and software standby

modes, refer to section 5.4, Displaying and Modifying the Contents of Memory.

3.5.3 Interrupts

During execution and step execution, the user can interrupt the MCU.

During halting emulation (break mode), the interrupt source is retained. The mode transits the interrupt

processing immediately after emulation is restarted.

3.5.4 Control Input Signals (_RES, _BREQ, and _WAIT)

The MCU control input signals are _RES, _BREQ, and _WAIT.

The _RES signal is only valid when emulation has been started with normal program execution (i.e., the _RES

signal is invalid when emulation has been started with step execution). While emulation is being halted (break),

the input of the _RES signal to the MCU is not possible. The input of the _RES signal during execution or step

execution is disabled by a setting in the [Configuration Properties] dialog box.

The _BREQ and _WAIT signals are always valid during emulation or emulation halted (break). The input of

those signals is disabled by a setting in the [Configuration Properties] dialog box.

3.5.5 Bus State Controller (BSC)

The wait state controller has a programmable wait mode and a WAIT pin input mode. The programmable wait

mode is valid when the emulation memory or user external memory is accessed, but input to the user WAIT pin

is only valid when user external memory is accessed.

3.5.6 Watchdog Timer (WDT)

While emulation is being halted (during break), counting up the WDT timer counter (TCNT) is suspended, and

restarted when emulation is executed again (user mode).

During break mode, a prescaler, which supplies a clock to TCNT, operates continuously. Since the phase of the

prescaler may be unmatched before or after emulation transits the break mode, the period before an overflow

occurs will differ by ±1 cycle in the prescaler’s clock cycle.

1 2 ... 67 68 69 70 71 72 73 74 75 76 77 ... 242 243

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Renesas User System Interface Board HS7047ECH61H Uživatelský manuál Strana 72