
M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
Rev.1.00 Oct 01, 2002 page 103 of 110
REJ03B0134-0100Z
Address 00EA16
Addresses 00EC16
b7 b6 b5 b4 b3 b2 b1 b0
OSD control register (CC) [Address 00EA
16
]
B Name
Functions After reset R
W
OSD Control Register
0
All-blocks display control
bit (CC0) (See note)
0 : All-blocks display off
1 : All-blocks display on
0
1 Block 1 display control bit
(CC1)
0 : Block 1 display off
1 : Block 1 display on
0
2
0 : Block 2 display off
1 : Block 2 display on
0
3
to
6
0
Note: Display is controlled by logical product (AND) between the all-blocks display
control bit and each block control bit.
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
Block 2 display control bit
(CC2)
RW
RW
RW
R—
7
0 : P1
0
1 : OUT2
0
P1
0
/OUT2 pin switch bit
(CC7)
RW
7
6
5
4
3
2
1
0
port contro
reg
ster
ress 00
16
a
m
e
u
n
c
t
o
n
s
ter reset
o
r
t
o
n
t
r
o
e
g
s
t
e
r
0
S
Y
N
C
n
p
u
t
p
o
a
r
t
y
s
w
i
t
c
h
b
i
t
(
H
S
Y
C
)
0
:
o
s
t
v
e
p
o
a
r
t
y
n
p
u
t
1
:
N
e
g
a
t
i
v
e
p
o
l
a
r
i
t
y
i
n
p
u
t
0
10
:
o
s
t
v
e
p
o
a
r
t
y
n
p
u
t
1
:
N
e
g
a
t
i
v
e
p
o
l
a
r
i
t
y
i
n
p
u
t
0
2
/
/
o
u
t
p
u
t
p
o
a
r
t
y
s
w
t
c
b
i
t
(
R
/
G
/
B
)
0
:
o
s
t
v
e
p
o
a
r
t
y
o
u
t
p
u
t
1
:
N
e
g
a
t
i
v
e
p
o
l
a
r
i
t
y
o
u
t
p
u
t
0
30
4
1
o
u
t
p
u
t
p
o
a
r
t
y
s
w
i
t
c
h
b
i
t
(
O
U
T
1
)
0
:
o
s
t
v
e
p
o
a
r
t
y
o
u
t
p
u
t
1
:
N
e
g
a
t
i
v
e
p
o
l
a
r
i
t
y
o
u
t
p
u
t
0
5
s
g
n
a
o
u
t
p
u
t
s
w
t
c
t
(
O
P
5
)
0
:
s
g
n
a
o
u
t
p
u
t
1
:
M
U
T
E
s
i
g
n
a
l
o
u
t
p
u
t
0
6
s
g
n
a
o
u
t
p
u
t
s
w
t
c
b
i
t
(
O
P
6
)
0
:
s
g
n
a
o
u
t
p
u
t
1
:
M
U
T
E
s
i
g
n
a
l
o
u
t
p
u
t
0
7
s
g
n
a
o
u
t
p
u
t
s
w
t
c
b
i
t
(
O
P
7
)
0
:
s
g
n
a
o
u
t
p
u
t
1
:
M
U
T
E
s
i
g
n
a
l
o
u
t
p
u
t
0
S
Y
N
C
n
p
u
t
p
o
a
r
t
y
s
w
i
t
c
h
b
i
t
(
V
S
Y
C
)
2
o
u
t
p
u
t
p
o
a
r
t
y
s
w
i
t
c
h
b
i
t
(
O
U
T
2
)
0
:
o
s
t
v
e
p
o
a
r
t
y
o
u
t
p
u
t
1
:
N
e
g
a
t
i
v
e
p
o
l
a
r
i
t
y
o
u
t
p
u
t
Komentáře k této Příručce