
M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
Rev.1.00 Oct 01, 2002 page 90 of 110
REJ03B0134-0100Z
State immediately after reset
b
7 b0b
7b0
HR0H
R
1H
R
2H
R
3HR4H
R
5
CV10C
V
1
1CV12CV13CV14C
V
1
5C
V
1
6
CV20CV21CV22CV23CV24CV25CV26
CS10C
S
1
1CS20CS21
MD10MD20
CO01CO02CO03C
O
0
5
CO11CO12CO13C
O
1
5
CO21CO22CO23CO25
CO31CO32CO33C
O
3
5
CC0C
C
1C
C
2
V
S
Y
CR/G/BOUT1
O
P
5O
P
6O
P
7
HSYC
CK0CK1
ADM0ADM1ADM2ADM4
ADC0A
D
C
1ADC2ADC4 ADC3A
D
C
5
34
0
3
4
1
34
2
34
3
34
4
12
0
1
2
1
12
2
12
3
12
4
CK0RE5 RE4 RE3
CM2
TM1RT
M
2
RTM3RTM4RCRTRV
S
C
RIT3R
CK0MSR
1T1R1T2R
S1R
T
M
1
ETM2ET
M
3
ETM4ECRTEV
S
C
EIT3E
1T1E1
T
2
E
S
1
EMSE
3
4
5
CK0
?
00
16
?
0 0 0 0 0 00
FF
16
07
16
FF
16
07
16
C
O
0
4
C
O
1
4
CO24
C
O
3
4
C
O
0
6
C
O
1
6
CO26
C
O
3
6
C
O
0
7
C
O
1
7
CO27
C
O
3
7
C
C
7
OUT2
I
I
C
R
I
I
C
E
F
0
1
6
F
1
1
6
F2
16
F3
16
F
4
1
6
F
5
1
6
F
6
1
6
F
7
1
6
F
8
1
6
F9
16
F
A
1
6
F
B
1
6
F
C
1
6
F
D
1
6
F
E
1
6
F
F
1
6
E
0
1
6
E
1
1
6
E
2
1
6
E
3
1
6
E
4
1
6
E5
16
E6
16
E7
16
E
8
1
6
E
9
1
6
E
B
1
6
E
C
1
6
ED
16
EE
16
E
F
1
6
E
A
1
6
A
d
d
r
e
s
s
O
S
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
C
C
)
O
S
D
p
o
r
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
C
R
T
P
)
A-D control register 1 (AD1)
A-D control register 2 (AD2)
Timer 1 (TM1)
V
e
r
t
i
c
a
l
r
e
g
i
s
t
e
r
2
(
C
V
2
)
C
o
l
o
r
r
e
g
i
s
t
e
r
0
(
C
O
0
)
Color register 1 (CO1)
C
h
a
r
a
c
t
e
r
s
i
z
e
r
e
g
i
s
t
e
r
(
C
S
)
B
o
r
d
e
r
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
M
D
)
Register
H
o
r
i
z
o
n
t
a
l
r
e
g
i
s
t
e
r
(
H
R
)
Vertical register 1 (CV1)
T
i
m
e
r
2
(
T
M
2
)
T
i
m
e
r
3
(
T
M
3
)
T
i
m
e
r
4
(
T
M
4
)
T
i
m
e
r
1
2
m
o
d
e
r
e
g
i
s
t
e
r
(
T
1
2
M
)
Timer 34 mode register (T34M)
P
W
M
5
r
e
g
i
s
t
e
r
(
P
W
M
5
)
I
n
t
e
r
r
u
p
t
i
n
p
u
t
p
o
l
a
r
i
t
y
r
e
g
i
s
t
e
r
(
R
E
)
Test register (TEST)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
I
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
(
I
C
O
N
2
)
Color register 2 (CO2)
C
o
l
o
r
r
e
g
i
s
t
e
r
3
(
C
O
3
)
O
S
D
c
l
o
c
k
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
C
K
)
CPU mode register (CPUM)
Bit allocation
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
000 0
0
111 110
0
0
00
00
16
0
000000
0
0
1
6
0
?
0
??????
???????
0
000????
?
0
0000?0?
?
?
?
0000000?
1 1111100
00
16
00
16
0
0
1
6
0
0
1
6
00
16
■
S
F
R
a
r
e
a
(
a
d
d
r
e
s
s
e
s
E
01
6
t
o
F
F1
6)
:
F
i
x
t
o
t
h
i
s
b
i
t
t
o
“
0
”
(
d
o
n
o
t
w
r
i
t
e
t
o
“
1
”
)
:
Function bit
:
No function bit
:
F
i
x
t
o
t
h
i
s
b
i
t
t
o
“
1
”
(
d
o
n
o
t
w
r
i
t
e
t
o
“
0
”
)
Name
:
:
“
0
”
i
m
m
e
d
i
a
t
e
l
y
a
f
t
e
r
r
e
s
e
t
0
1
?
:
“
1
”
i
m
m
e
d
i
a
t
e
l
y
a
f
t
e
r
r
e
s
e
t
1
0
<
B
i
t
a
l
l
o
c
a
t
i
o
n
><
S
t
a
t
e
i
m
m
e
d
i
a
t
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