
M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
Rev.1.00 Oct 01, 2002 page 33 of 110
REJ03B0134-0100Z
8.6.2 I
2
C Address Register
The I
2
C address register (address 00D816) consists of a 7-bit slave
address and a read/write bit. In the addressing mode, the slave ad-
dress written in this register is compared with the address data to be
received immediately after the START condition are detected.
(1) Bit 0: read/write bit (RBW)
Not used when comparing addresses, in the 7-bit addressing mode.
In the 10-bit addressing mode, the first address data to be received
is compared with the contents (SAD6 to SAD0 + RBW) of the I
2
C
address register.
The RBW bit is cleared to “0” automatically when the stop condition
is detected.
(2) Bits 1 to 7: slave address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit address-
ing mode and the 10-bit addressing mode, the address data trans-
mitted from the master is compared with the contents of these bits.
Fig. 8.6.3 I
2
C Address Register
7
6
5
4
3
2
1
0
0
ea
/wr
te
t
(RBW)
1
t
o
7
ave a
ress
(SAD0 to SAD6)
<
n
y
n
1
0
-
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p
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0
:
W
a
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f
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l
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R
T
c
o
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d
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n
(
r
e
a
d
s
t
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)
1
:
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l
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R
E
S
T
A
R
T
c
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d
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t
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n
(
w
r
i
t
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s
t
a
t
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)
<
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t
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>
T
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I
2
C
A
d
d
r
e
s
s
R
e
g
i
s
t
e
r
I
2
C address register (S0D) [Address 00D8
16
]
N
a
m
Function
0
0
A
f
t
e
r
r
e
s
e
t
R
R—
R
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