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M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
Rev.1.00 Oct 01, 2002 page 81 of 110
REJ03B0134-0100Z
Max.
6
2
3
4
Min.
1
Typ.
2.5
13. A-D COMPARISON CHARACTERISTICS
(VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = 10 °C to 70 °C, unless otherwise noted)
Resolution
Absolute accuracy
Max.
6
±2
bits
LSB
Min.
0
Limits
UnitTest conditionsParameterSymbol
Typ.
±1
15. MULTI-MASTER I
2
C-BUS BUS LINE CHARACTERISTICS
Bus free time
Hold time for START condition
LOW period of SCL clock
Rising time of both SCL and SDA signals
Data hold time
HIGH period of SCL clock
Falling time of both SCL and SDA signals
Data set-up time
Set-up time for repeated START condition
Set-up time for STOP condition
tBUF
tHD; STA
tLOW
tR
tHD; DAT
tHIGH
tF
tSU; DAT
tSU; STA
tSU; STO
Max.
1000
300
Min.
1.3
0.6
1.3
20+0.1Cb
0
0.6
20+0.1Cb
100
0.6
0.6
Max.
300
0.9
300
µs
µs
µs
ns
µs
µs
ns
ns
µs
µs
Unit
Standard clock mode High-speed clock mode
ParameterSymbol
Note: Cb = total capacitance of 1 bus line
Fig.15.1 Definition Diagram of Timing on Multi-master I
2
C-BUS
Min.
4.7
4.0
4.7
0
4.0
250
4.7
4.0
SDA
SCL
P
tBUF
S
tHD;STA
tLOW
tR
tHD;DAT tHIGH
tF
tSU;DAT tSU;STA
Sr
P
tSU;STO
tHD;STA
S
Sr
P
: Start condition
: Restart condition
: Stop condition
14. D-A CONVERSION CHARACTERISTICS
(VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = 10 °C to 70 °C, unless otherwise noted)
Resolution
Absolute accuracy
Setting time
Output resistor
bits
LSB
µs
k
Limits
UnitTest conditionsParameterSymbol
tsu
Ro
Note: Only M37221EASP/FP have a built-in D-A converter.
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