Renesas Renasas Single-Chip Microcomputer SH7086 Uživatelský manuál stáhnout pdf (Strana 269)

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Chapter 5 Interrupt

FSET I

Time

5.2 Interrupt Control

The following explains how to enable/disable maskable interrupts and set acknowledge priority. The expla-

nation here does not apply to non-maskable interrupts.

Maskable interrupts are enabled and disabled by using the interrupt enable flag (I flag), interrupt priority

level select bit, and processor interrupt priority level (IPL). Whether there is any interrupt requested is

indicated by the interrupt request bit. The interrupt request bit and interrupt priority level select bit are

arranged in the interrupt control register provided for each specific interrupt. The interrupt enable flag (I

flag) and processor interrupt priority level (IPL) are arranged in the flag register (FLG).

For details about the memory allocation and the configuration of interrupt control registers, refer to the

M16C User's Manual.

5.2.1 Interrupt Enable Flag (I Flag)

The interrupt enable flag (I flag) is used to disable/enable maskable interrupts. When this flag is set (=

1), all maskable interrupts are enabled; when the flag is cleared to 0, they are disabled. This flag is

automatically cleared to 0 after a reset is cleared.

When the I flag is changed, the altered flag status is reflected in determining whether or not to accept an

interrupt request at the following timing:

• If the flag is changed by an REIT instruction, the changed status takes effect beginning with that

REIT instruction.

• If the flag is changed by an FCLR, FSET, POPC, or LDC instruction, the changed status takes

effect beginning with the next instruction.

instruction

Interrupt sequence

REIT

Interrupt sequence

Next instruction

instruction

Time

Figure 5.2.1 Timing at which changes of I flag are reflected in interrupt handling

Interrupt request generated

5.2 Interrupt Control

When changed by REIT instruction

Determination whether or not to

accept interrupt request

Determination whether or not to

accept interrupt request

When changed by FCLR, FSET, POPC, or LDC instruction

(If I flag is changed from 0 to 1 by REIT instruction)

(If I flag is changed from 0 to 1 by FSET instruction)

5.2.2 Interrupt Request Bit

This bit is set (= 1) when an interrupt request is generated. This bit remains set until the interrupt request

is acknowledged. The bit is cleared to 0 when the interrupt request is acknowledged.

This bit can be cleared to 0 (but cannot be set to 1) in software.

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