Renesas Renasas Single-Chip Microcomputer SH7086 Uživatelský manuál stáhnout pdf (Strana 287)

269

Calculation number of cycles

6.1

Instruction queue buffer

Sample program

Address Code Instruction

FC06C 64 JMP TEST_11

FC06D 04 NOP

FC06E 04 NOP

FC06F 04 NOP

FC070 04 NOP

FC071 04 NOP

FC072 TEST_11:

FC072 73FF00400240 MOV.W 04000h, 04002h

FC078 64 JMP TEST_12

FC079 04 NOP

FC07A 04 NOP

FC07B 04 NOP

FC07C 04 NOP

FC07D 04 NOP

FC07E TEST_12:

Content at jump address is

prefetched at the same time

the instruction queue buffer is

cleared.

Fetch code

73FF 64

JMP TEST_11 MOV.W JMP TEST_12

Instructions

under execution

Instruction

queue buffer

04 04

73 00 0404 04

04 04 04

FF FF 40 04 04 04

0402000404

04 0404

7373

F1 F1

PPPP P

Address bus

Data bus (H)

Data bus (L)

DR : Indicates a data read.

FC06E FC072 04000

73 00

FF 40

FC074

FC080

BCLK

: Indicates the locations of the instruction queue buffer that are cleared.

Content at jump address is

prefetched at the same time

the instruction queue buffer

is cleared.

Jump address

40 40

FC07E

0040

FC076

FC07A

P : Indicates a prefetch (reading from memory into the instruction queue buffer).

Address from which to read data

04002

Address from which to write data

0240

0FC078

DW : Indicates a data write.

Content at address 4001

Content at address 4000

The instruction

queue buffer is

emptied, so one

more cycle is waited.

Fetch

FetchFetch

Fetch

Sample program

Address Code Instruction

FC150 64 JMP TEST_11

FC151 04 NOP

FC152 04 NOP

FC153 04 NOP

FC154 04 NOP

FC155 04 NOP

FC156 TEST_11:

FC156 73F10040 MOV.W 04000h, R1

FC15A 64 JMP TEST_12

FC15B 04 NOP

FC15C 04 NOP

FC15D 04 NOP

FC15E 04 NOP

FC15F 04 NOP

FC160 TEST_12:

Content at jump address is prefetched at

the same time the instruction queue buffer

is cleared.

Fetch code

73F1 64

JMP TEST_11 MOV.W JMP TEST_12

Instructions

under execution

Instruction

queue buffer

04 04

73 64 0404 04

04 04 04

F1 F1 04 04 04

04000404

04 0404

7373

FF FF

Address bus

Data bus (H)

Data bus (L)

DR : Indicates a data read.

FC152 FC156

04000

73 00

F1 40

FC158

BCLK

: Indicates the locations of the instruction queue buffer that are cleared.

Content at jump address is

prefetched at the same time

the instruction queue buffer

is cleared.

Jump address

FC162

FC160

0040

FC15A

P : Indicates a prefetch (reading from memory into the instruction queue buffer).

Address from which

to read data

FC15C

DW : Indicates a data write.

1 wait

Content at address 4001

Content at address 4000

Fetch Fetch Fetch

Figure 6.1.5.

When executing an instruction to transfer data between even addresses starting from an even address

(Program area: 16-bit bus without wait state; Data area: 16-bit bus without wait state)

Figure 6.1.6. When executing an instruction to read from even addresses starting from an even address

(Program area: 16-bit bus without wait state; Data area: 16-bit bus with wait state)

1 2 ... 282 283 284 285 286 287 288 289 290 291 292 ... 307 308

Komentáře k této Příručce

Žádné komentáře

Renesas Renasas Single-Chip Microcomputer SH7086 Uživatelský manuál Strana 287

Komentáře k této Příručce

Související produkty a manuály pro Sítě Renesas Renasas Single-Chip Microcomputer SH7086