Renesas R8C/Tiny Series Manuál

RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTERM16C FAMILY / R8C /Tiny SERIESR8C/10 Group16Rev. 1.20Revision date: Jan 27, 2006Hardware Manualwww.renesas.com

B-2SFR Page ReferenceA d d r e s s R e g i s t e rS y m b o l P a g e0 0 8 01 60 0 8 11 60 0 8 21 60 0 8 31 60 0 8 41 60 0 8 51 60 0 8 61 60 0 8 71 6

R8C/10 Group 13. Serial InterfaceIRev.1.20 Jan 27, 2006 page 90 of 180REJ09B0019-0120i = 0 , 1S P : S t o p b i tP A R : P a r i t y b

R8C/10 Group 13. Serial InterfaceRev.1.20 Jan 27, 2006 page 91 of 180REJ09B0019-0120Figure 13.3 U0TB and U1TB Registers, U0RB and U1RB Register

R8C/10 Group 13. Serial InterfaceIRev.1.20 Jan 27, 2006 page 92 of 180REJ09B0019-0120U A R T i t r a n s m i t / r e c e i v e m o d e r e

R8C/10 Group 13. Serial InterfaceRev.1.20 Jan 27, 2006 page 93 of 180REJ09B0019-0120U A R T i t r a n s m i t / r e c e i v e c o n t r o l

R8C/10 Group 13.1 Clock Synchronous Serial I/O ModeRev.1.20 Jan 27, 2006 page 94 of 180REJ09B0019-012013.1 Clock Synchronous Serial I/O ModeThe

R8C/10 Group 13.1 Clock Synchronous Serial I/O ModeRev.1.20 Jan 27, 2006 page 95 of 180REJ09B0019-0120Table 13. 2 Registers to Be Used and Sett

R8C/10 Group 13.1 Clock Synchronous Serial I/O ModeRev.1.20 Jan 27, 2006 page 96 of 180REJ09B0019-0120Figure 13.6 Transmit and Receive Operatio

R8C/10 Group 13.1 Clock Synchronous Serial I/O ModeRev.1.20 Jan 27, 2006 page 97 of 180REJ09B0019-012013.1.1 Polarity Select FunctionFigure 13.7

R8C/10 Group 13.1 Clock Synchronous Serial I/O ModeRev.1.20 Jan 27, 2006 page 98 of 180REJ09B0019-012013.1.3 Continuous Receive ModeThe unit is

R8C/10 Group 13.2 Clock Asynchronous Serial I/O (UART) ModeRev.1.20 Jan 27, 2006 page 99 of 180REJ09B0019-0120Item SpecificationTransfer data fo

R8C/10 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTERRev.1.20 Jan 27, 2006 page 1 of 180REJ09B0019-0120REJ09B0019-0120Rev.1.20Jan 27, 20061. Overvie

R8C/10 Group 13.2 Clock Asynchronous Serial I/O (UART) ModeRev.1.20 Jan 27, 2006 page 100 of 180REJ09B0019-0120Table 13.5 Registers to Be Used

R8C/10 Group 13.2 Clock Asynchronous Serial I/O (UART) ModeRev.1.20 Jan 27, 2006 page 101 of 180REJ09B0019-0120TxDiTransfer clockUiC1 registerTE

R8C/10 Group 13.2 Clock Asynchronous Serial I/O (UART) ModeRev.1.20 Jan 27, 2006 page 102 of 180REJ09B0019-0120• Example of receive timing when

R8C/10 Group 13.2 Clock Asynchronous Serial I/O (UART) ModeRev.1.20 Jan 27, 2006 page 103 of 180REJ09B0019-012013.2.3 Bit RateDivided-by-16 of f

R8C/10 GroupRev.1.20 Jan 27, 2006 page 104 of 180REJ09B0019-012014. A/D ConverterThe A/D converter consists of one 10-bit successive approximatio

R8C/10 GroupRev.1.20 Jan 27, 2006 page 105 of 180REJ09B0019-01201/2φAD1/2fA DA/D conversion rate selectionC K S 1 = 1C K S 0 = 0AD registerResist

R8C/10 GroupRev.1.20 Jan 27, 2006 page 106 of 180REJ09B0019-0120A D c o n t r o l r e g i s t e r 0(1 )S y m b o lA d d r e s sA f t e r

R8C/10 GroupRev.1.20 Jan 27, 2006 page 107 of 180REJ09B0019-0120Figure 14.3 ADCON2 Register and AD Register14. A/D ConverterA D c o n t r o l

R8C/10 GroupRev.1.20 Jan 27, 2006 page 108 of 180REJ09B0019-012014.1 One-shot ModeIn one-shot mode, the input voltage on one selected pin is A/D

R8C/10 GroupRev.1.20 Jan 27, 2006 page 109 of 180REJ09B0019-012014.2 Repeat ModeIn repeat mode, the input voltage on one selected pin is A/D con

Rev.1.20 Jan 27, 2006 page 2 of 180REJ09B0019-0120R8C/10 Group1. OverviewTable 1.1 Performance outline1.2 Performance OverviewTable 1.1. lists

R8C/10 GroupRev.1.20 Jan 27, 2006 page 110 of 180REJ09B0019-012014.3 Sample and HoldIf the SMP bit in the ADCON2 register is set to “1” (with sa

R8C/10 GroupRev.1.20 Jan 27, 2006 page 111 of 180REJ09B0019-012014.5 Internal Equivalent Circuit of Analog Input14.5 Internal Equivalent Circui

R8C/10 GroupRev.1.20 Jan 27, 2006 page 112 of 180REJ09B0019-012014.6 Inflow Current Bypass Circuit14.6 Inflow Current Bypass CircuitFigure 14.9

R8C/10 GroupRev.1.20 Jan 27, 2006 page 113 of 180REJ09B0019-012014.7 Output Impedance of Sensor under A/D ConversionTo carry out A/D conversion

R8C/10 GroupRev.1.20 Jan 27, 2006 page 114 of 180REJ09B0019-0120Figure 14.11 Analog Input Pin and External Sensor Equivalent CircuitR0R ( 2 . 8

R8C/10 Group 15. Programmable I/O PortsRev.1.20 Jan 27, 2006 page 115 of 180REJ09B0019-012015. Programmable I/O Ports15. 1 DescriptionThe progra

R8C/10 Group 15. Programmable I/O PortsRev.1.20 Jan 27, 2006 page 116 of 180REJ09B0019-0120Figure 15.1 Programmable I/O Ports (1)D a t a b u s

R8C/10 Group 15. Programmable I/O PortsRev.1.20 Jan 27, 2006 page 117 of 180REJ09B0019-0120Figure 15.2 Programmable I/O Ports (2)" 1 "

R8C/10 Group 15. Programmable I/O PortsRev.1.20 Jan 27, 2006 page 118 of 180REJ09B0019-0120Figure 15.3 Programmable I/O Ports (3)P 45P 32, P 3

R8C/10 Group 15. Programmable I/O PortsRev.1.20 Jan 27, 2006 page 119 of 180REJ09B0019-0120Figure 15.4 Programmable I/O Port (4)D a t a b u sD

Rev.1.20 Jan 27, 2006 page 3 of 180REJ09B0019-0120R8C/10 Group1. Overview1.3 Block DiagramFigure 1.1 shows this MCU block diagram.Figure 1.1 B

R8C/10 Group 15. Programmable I/O PortsRev.1.20 Jan 27, 2006 page 120 of 180REJ09B0019-0120P o r t P i r e g i s t e r ( i = 0 , 1 ,

R8C/10 Group 15. Programmable I/O PortsRev.1.20 Jan 27, 2006 page 121 of 180REJ09B0019-0120P u l l - u p c o n t r o l r e g i s t e r 0Sy

R8C/10 Group 15. Programmable I/O PortsRev.1.20 Jan 27, 2006 page 122 of 180REJ09B0019-0120PD0PD0_10001PUR0PU00010XADCON0CH2, CH1, CH0XXXXXX1102

R8C/10 Group 15. Programmable I/O PortsRev.1.20 Jan 27, 2006 page 123 of 180REJ09B0019-0120PD0PD0_40001PUR0PU01010XADCON0CH2, CH1, CH0XXXXXX0112

R8C/10 Group 15. Programmable I/O PortsRev.1.20 Jan 27, 2006 page 124 of 180REJ09B0019-0120_____Table 15.10 Port P11/KI1 SettingRegisterBitSetti

R8C/10 Group 15. Programmable I/O PortsRev.1.20 Jan 27, 2006 page 125 of 180REJ09B0019-0120Table 15.13 Port P14/TXD0 SettingRegisterBitSetting v

R8C/10 Group 15. Programmable I/O PortsRev.1.20 Jan 27, 2006 page 126 of 180REJ09B0019-0120____________Table 15.17 Port P30/CNTR0 SettingRegiste

R8C/10 Group 15. Programmable I/O PortsRev.1.20 Jan 27, 2006 page 127 of 180REJ09B0019-0120Table 15.21 Port P37/TXD10/RXD1 SettingRegisterBitSet

R8C/10 Group 15. Programmable I/O PortsRev.1.20 Jan 27, 2006 page 128 of 180REJ09B0019-0120P i n n a m eC o n n e c t i o nP o r t s P 0 ,

R8C/10 Group 16. Electrical CharacteristicsRev.1.20 Jan 27, 2006 page 129 of 180REJ09B0019-012016. Electrical CharacteristicsTable 16.1 Absolut

Rev.1.20 Jan 27, 2006 page 4 of 180REJ09B0019-0120R8C/10 Group1. Overview1.4 Product InformationTable 1.2 lists the product inforamation.Table

R8C/10 Group 16. Electrical CharacteristicsRev.1.20 Jan 27, 2006 page 130 of 180REJ09B0019-0120Table 16.3 A/D Conversion CharacteristicsStandar

R8C/10 Group 16. Electrical CharacteristicsRev.1.20 Jan 27, 2006 page 131 of 180REJ09B0019-0120Figure 16.1 Port P0 to P4 measurement circuitP0P

R8C/10 Group 16. Electrical CharacteristicsRev.1.20 Jan 27, 2006 page 132 of 180REJ09B0019-0120Table 16.6 Electrical Characteristics (1) [V

R8C/10 Group 16. Electrical CharacteristicsRev.1.20 Jan 27, 2006 page 133 of 180REJ09B0019-0120Table 16.7 Electrical Characteristics (2) [V

R8C/10 Group 16. Electrical CharacteristicsRev.1.20 Jan 27, 2006 page 134 of 180REJ09B0019-0120Timing requirements (Unless otherwise noted: VCC

R8C/10 Group 16. Electrical CharacteristicsRev.1.20 Jan 27, 2006 page 135 of 180REJ09B0019-0120Figure 16.3 Vcc=5V timing diagramCLKiTxDiRxDiINT

R8C/10 Group 16. Electrical CharacteristicsRev.1.20 Jan 27, 2006 page 136 of 180REJ09B0019-0120Table 16.13 Electrical Characteristics (3) [

R8C/10 Group 16. Electrical CharacteristicsRev.1.20 Jan 27, 2006 page 137 of 180REJ09B0019-0120Table 16.14 Electrical Characteristics (4) [

R8C/10 Group 16. Electrical CharacteristicsRev.1.20 Jan 27, 2006 page 138 of 180REJ09B0019-0120Timing requirements (Unless otherwise noted: VCC

R8C/10 Group 16. Electrical CharacteristicsRev.1.20 Jan 27, 2006 page 139 of 180REJ09B0019-0120Figure 16.4 Vcc=3V timing diagramCLKiTxDiRxDiINT

Rev.1.20 Jan 27, 2006 page 5 of 180REJ09B0019-0120R8C/10 Group1. OverviewPackage: PLQP0032GB-A (32P6U-A)Figure 1.3 Pin Assignments (Top View)P

R8C/10 Group 17. Memory MapRev.1.20 Jan 27, 2006 page 140 of 180REJ09B0019-0120Table 17.1 Flash Memory Version Performance17. Flash Memory Versi

17. Flash Memory VersionR8C/10 GroupRev.1.20 Jan 27, 2006 page 141 of 180REJ09B0019-012017.2 Memory MapThe ROM in the flash memory version is se

R8C/10 GroupRev.1.20 Jan 27, 2006 page 142 of 180REJ09B0019-012017.3 Functions To Prevent Flash Memory from RewritingTo prevent the flash memory

R8C/10 GroupRev.1.20 Jan 27, 2006 page 143 of 180REJ09B0019-012017.4 CPU Rewrite ModeIn CPU rewrite mode, the user ROM area can be rewritten by e

R8C/10 GroupRev.1.20 Jan 27, 2006 page 144 of 180REJ09B0019-012017.4.1 EW0 ModeThe microcomputer is placed in CPU rewrite mode by setting the FMR

R8C/10 GroupRev.1.20 Jan 27, 2006 page 145 of 180REJ09B0019-0120Figure 17.3 shows the FMR0 register. Figure 17.4 shows the FMR1 and FMR4 register

R8C/10 GroupRev.1.20 Jan 27, 2006 page 146 of 180REJ09B0019-0120Flash memory control register 0S y m b o lA d d r e s sA f t e r r e s e tF M R

R8C/10 GroupRev.1.20 Jan 27, 2006 page 147 of 180REJ09B0019-0120Figure 17.4 FMR1 and FMR4F l a s h m e m o r y c o n t r o l r e g i s t e

R8C/10 GroupRev.1.20 Jan 27, 2006 page 148 of 180REJ09B0019-0120Figure 17.7 Setting and Resetting of EW1 ModeS e t C M 0 a n d C M 1 r e

R8C/10 GroupRev.1.20 Jan 27, 2006 page 149 of 180REJ09B0019-0120Figure 17.8 Process to Reduce Power Consumption in On-Chip Oscillator Mode (Main

Rev.1.20 Jan 27, 2006 page 6 of 180REJ09B0019-0120R8C/10 Group1. OverviewSignal name Pin name I/O typePower supply Vcc, Iinput VssIVcc IVcc OAna

R8C/10 GroupRev.1.20 Jan 27, 2006 page 150 of 180REJ09B0019-012017.4.3 Software CommandsSoftware commands are described below. The command code a

R8C/10 GroupRev.1.20 Jan 27, 2006 page 151 of 180REJ09B0019-0120Start Program completedYESNOWrite the command code ‘4016’ to the write addressWri

R8C/10 GroupRev.1.20 Jan 27, 2006 page 152 of 180REJ09B0019-0120Write ‘D016’ to the given block addressStart Block erase completedYESNOWrite the

R8C/10 GroupRev.1.20 Jan 27, 2006 page 153 of 180REJ09B0019-0120Figure 17.11 Block Erase Command (When Using Erase-suspend Function)Write ‘D016’

R8C/10 GroupRev.1.20 Jan 27, 2006 page 154 of 180REJ09B0019-012017.4.4 Status RegisterThe status register indicates the operating status of the f

R8C/10 GroupRev.1.20 Jan 27, 2006 page 155 of 180REJ09B0019-012017.4.5 Full Status CheckWhen an error occurs, the FMR06 to FMR07 bits in the FMR0

R8C/10 GroupRev.1.20 Jan 27, 2006 page 156 of 180REJ09B0019-0120F u l l s t a t u s c h e c kF M R 0 6 = 1a n d F M R 0 7 = 1 ?N oY e sFMR

R8C/10 Group 17.5 Standard Serial I/O ModeRev.1.20 Jan 27, 2006 page 157 of 180REJ09B0019-012017.5 Standard Serial I/O ModeIn standard serial I/

R8C/10 Group 17.5 Standard Serial I/O ModeRev.1.20 Jan 27, 2006 page 158 of 180REJ09B0019-0120P i n DescriptionVC C, VS SA p p l y t h e v o

R8C/10 Group 17.5 Standard Serial I/O ModeRev.1.20 Jan 27, 2006 page 159 of 180REJ09B0019-0120Figure 17.13 Pin Connections for Standard Serial I

R8C/10 Group 2. Central Processing Unit (CPU)Rev.1.20 Jan 27, 2006 page 7 of 180REJ09B0019-01202. Central Processing Unit (CPU)Figure 2.1 shows

R8C/10 Group 17.5 Standard Serial I/O ModeRev.1.20 Jan 27, 2006 page 160 of 180REJ09B0019-0120Data inputData outputTxDCNVssRxDMicrocomputer(1) I

R8C/11 Group 18. On-chip DebuggerRev.1.20 Jan 27, 2006 page 161 of 180REJ09B0019-012018. On-chip debuggerThe microcomputer has functions to exe

R8C/10 Group 19. Usage NotesRev.1.20 Jan 27, 2006 page 162 of 180REJ09B0019-012019. Usage Notes19.1 Stop Mode and Wait Mode19.1.1 Stop ModeWhen

R8C/10 Group 19. Usage NotesRev.1.20 Jan 27, 2006 page 163 of 180REJ09B0019-012019.2 Interrupt19.2.1 Reading Address 0000016Do not read the addr

R8C/10 Group 19. Usage NotesRev.1.20 Jan 27, 2006 page 164 of 180REJ09B0019-0120Figure 19.1 Example of Procedure for Changing Interrupt FactorD

R8C/10 Group 19. Usage NotesRev.1.20 Jan 27, 2006 page 165 of 180REJ09B0019-0120Example 1: Use NOP instructions to prevent I flag being set to “

R8C/10 Group 19. Usage NotesRev.1.20 Jan 27, 2006 page 166 of 180REJ09B0019-012019.3 Clock Generation Circuit19.3.1 Oscillation Stop Detection F

R8C/10 Group 19. Usage NotesRev.1.20 Jan 27, 2006 page 167 of 180REJ09B0019-012019.4 Timers19.4.1 Timers X, Y and Z(1) Timers X, Y and Z stop co

R8C/10 Group 19. Usage NotesRev.1.20 Jan 27, 2006 page 168 of 180REJ09B0019-012019.5 Serial Interface(1) When reading data from the UiRB (i=0,1)

R8C/10 Group 19. Usage NotesRev.1.20 Jan 27, 2006 page 169 of 180REJ09B0019-012019.6 A/D Converter(1) When writing to each bit but except bit 6

R8C/10 Group 2. Central Processing Unit (CPU)Rev.1.20 Jan 27, 2006 page 8 of 180REJ09B0019-01202.2 Address Registers (A0 and A1)A0 is a 16-bit

R8C/10 Group 19. Usage NotesRev.1.20 Jan 27, 2006 page 170 of 180REJ09B0019-012019.7 Flash Memory Version19.7.1 CPU Rewrite Mode● Operation Spee

R8C/10 Group 19. Usage NotesRev.1.20 Jan 27, 2006 page 171 of 180REJ09B0019-0120● InterruptTable 19.1 list the Interrupt in EW0 Mode and Table 1

R8C/10 Group 19. Usage NotesRev.1.20 Jan 27, 2006 page 172 of 180REJ09B0019-0120ModeEW1StatusDuring auto-matic erasing(erase-sus-pend func-tion

R8C/10 Group 19. Usage NotesRev.1.20 Jan 27, 2006 page 173 of 180REJ09B0019-012019.8 Noise(1) Bypass Capacitor between VCC and VSS PinsInsert a

R8C/10 Group 20. Usage Notes for On-chip DebuggerRev.1.20 Jan 27, 2006 page 174 of 180REJ09B0019-012020. Usage notes for on-chip debuggerWhen u

R8C/10 Group Appendix 1. Package DimensionsRev.1.20 Jan 27, 2006 page 175 of 180REJ09B0019-0120Appendix 1. Package Dimensions2.1. DIMENSIONS &q

R8C/10 GroupAppendix 2. Connecting Examples for Serial Writer and On-chip Debugging EmulatorRev.1.20 Jan 27, 2006 page 176 of 180REJ09B0019-0120

R8C/10 GroupAppendix 2. Connecting Examples for Serial Writer and On-chip Debugging EmulatorRev.1.20 Jan 27, 2006 page 177 of 180REJ09B0019-0120

R8C/10 Group Appendix 3. Package DimensionsRev.1.20 Jan 27, 2006 page 178 of 180REJ09B0019-0120Appendix 3. Example of Oscillation Evaluation Ci

R8C/10 Group Register IndexRev.1.20 Jan 27, 2006 page 179 of 180REJ09B0019-0120Register IndexAAD 107ADCON0 106, 108, 109ADCON1 106, 108, 109ADCON

R8C/10 Group 3. MemoryRev.1.20 Jan 27, 2006 page 9 of 180REJ09B0019-01203. MemoryFigure 3.1 is a memory map of this MCU. This MCU provides 1-Mb

R8C/10 Group Register IndexRev.1.20 Jan 27, 2006 page 180 of 180REJ09B0019-0120TZSC 74UU0BRG 91U0C0 92U0C1 93U0MR 92U0RB 91U0TB 91U1BRG 91U1C0 92

C-1REVISION HISTORYRev. Date DescriptionPage SummaryR8C/10 Group Hardware Manual0.91 Sep 8, 2003 First edition issued – 0.92 Nov 5, 2003Table1.1

C-2REVISION HISTORYRev. Date DescriptionPage SummaryR8C/10 Group Hardware Manual 0.92 Nov 5, 2003Table 12.12 revisedFigure 12.28 Add “Sampling cloc

C-3REVISION HISTORYRev. Date DescriptionPage SummaryR8C/10 Group Hardware Manual 0.92 Nov 5, 2003Section 17.5 Add sentencesTable 17.7 Rev

C-4REVISION HISTORYRev. Date DescriptionPage SummaryR8C/10 Group Hardware ManualTable 12.9 revisedTable 12.10 revised, NOTES revisedTable 12.11 revise

C-5REVISION HISTORYRev. Date DescriptionPage SummaryR8C/10 Group Hardware Manual1.10Apr.27.20054 Table 1.2, Figure 1.2 package name revised5 Figure 1.

C-6REVISION HISTORYRev. Date DescriptionPage SummaryR8C/10 Group Hardware Manual1.20Jan.27.20062 Table 1.1 Performance outline revised3 Figure 1.1 Blo

C-7REVISION HISTORYRev. Date DescriptionPage SummaryR8C/10 Group Hardware Manual1.20Jan.27.2006113 14.7 Output Impedance of Sensor under A/D Conversi

RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTERHARDWARE MANUALR8C/10 GroupPublication Data : Rev.0.93 Feb 18, 2004Rev.1.20 Jan 27, 2006Published by : Sales

R8C/10 GroupHardware Manual2-6-2, Ote-machi, Chiyoda-ku, Tokyo,100-0004, Japan

Keep safety first in your circuit designs!Notes regarding these materials1.Renesas Technology Corp. puts the maximum effort into making semiconductor

R8C/10 Group 4. Special Function Register (SFR)Rev.1.20 Jan 27, 2006 page 10 of 180REJ09B0019-0120Watchdog timer start register WDTS XX16W a t c

R8C/10 Group 4. Special Function Register (SFR)Rev.1.20 Jan 27, 2006 page 11 of 180REJ09B0019-0120UART0 transmit interrupt control register S0TI

R8C/10 Group 4. Special Function Register (SFR)Rev.1.20 Jan 27, 2006 page 12 of 180REJ09B0019-01200 0 8 01 60 0 8 11 60 0 8 21 60 0 8 31 60 0 8

R8C/10 Group 4. Special Function Register (SFR)Rev.1.20 Jan 27, 2006 page 13 of 180REJ09B0019-01200 0 C 01 60 0 C 11 60 0 C 21 60 0 C 31 60 0 C

R8C/10 Group 5. ResetRev.1.20 Jan 27, 2006 page 14 of 180REJ09B0019-01205. ResetThere are three types of resets: a hardware reset, a software re

R8C/10 Group 5. ResetRev.1.20 Jan 27, 2006 page 15 of 180REJ09B0019-0120Figure 5.2 Reset SequenceFigure 5.1 CPU Register Status After Resetb15

R8C/10 Group 5. ResetRev.1.20 Jan 27, 2006 page 16 of 180REJ09B0019-0120Figure 5.3 Example Reset CircuitFigure 5.4 Example Reset Circuit (Volt

R8C/10 GroupRev.1.20 Jan 27, 2006 page 17 of 180REJ09B0019-0120• C P U c l o c k s o u r c e• P e r i p h e r a l f u n c t i o n c l

R8C/10 GroupRev.1.20 Jan 27, 2006 page 18 of 180REJ09B0019-0120C P U c l o c kI n t e r r u p t r e q u e s t l e v e l j u d g m e n t

R8C/10 GroupRev.1.20 Jan 27, 2006 page 19 of 180REJ09B0019-0120S y s t e m c l o c k c o n t r o l r e g i s t e r 0(1 )S y m b o lA d d

How to Use This Manual1. IntroductionThis hardware manual provides detailed information on the R8C/10 Group of microcomputers.Users are expected to ha

R8C/10 GroupRev.1.20 Jan 27, 2006 page 20 of 180REJ09B0019-0120R WR WR WR Ob 7b 6b 5b 4b 3b 2b 1b 0O C D 0O C D 1O C D 2O C D 30000O s c i l l a

R8C/10 GroupRev.1.20 Jan 27, 2006 page 21 of 180REJ09B0019-0120Microcomputer(Built-in feedback resistor)XINXOUTE x t e r n a l l y d e r i v e

R8C/10 GroupRev.1.20 Jan 27, 2006 page 22 of 180REJ09B0019-01206.2 On-Chip Oscillator ClockThis clock, approximately 125 kHz, is supplied by the

R8C/10 GroupRev.1.20 Jan 27, 2006 page 23 of 180REJ09B0019-01206.3 CPU Clock and Peripheral Function ClockThere are two types of clocks: CPU cloc

R8C/10 GroupRev.1.20 Jan 27, 2006 page 24 of 180REJ09B0019-0120M o d e s O C D r e g i s t e rO C D 2C M 1 r e g i s t e rC M 1 7 , C M

R8C/10 GroupRev.1.20 Jan 27, 2006 page 25 of 180REJ09B0019-01206.4.2 Wait ModeIn wait mode, the CPU clock is turned off, so are the CPU and the w

R8C/10 GroupRev.1.20 Jan 27, 2006 page 26 of 180REJ09B0019-01206.4.3 Stop ModeIn stop mode, all oscillator circuits are turned off, so are the CP

R8C/10 GroupRev.1.20 Jan 27, 2006 page 27 of 180REJ09B0019-0120Figure 6.5 State Transition of Power ControlFigure 6.5 shows the state transition

R8C/10 GroupRev.1.20 Jan 27, 2006 page 28 of 180REJ09B0019-01206.5 Oscillation Stop Detection FunctionThe oscillation stop detection function is

R8C/10 GroupRev.1.20 Jan 27, 2006 page 29 of 180REJ09B0019-0120 Generated Interrupt Factor Bit showing interrupt factorOscillation stop dete

Document3. M16C Family DocumentsThe following documents were prepared for the M16C family.(1)ContentsShort SheetData SheetHardware ManualSoftware Manu

R8C/10 Group 7. ProtectionRev.1.20 Jan 27, 2006 page 30 of 180REJ09B0019-01207. ProtectionIn the event that a program runs out of control, this

R8C/10 Group 8. Processor ModeRev.1.20 Jan 27, 2006 page 31 of 180REJ09B0019-01208. Processor Mode8.1 Types of Processor ModeThe processor mode

R8C/10 Group 9. BusRev.1.20 Jan 27, 2006 page 32 of 180REJ09B0019-01209. BusDuring access, the ROM/RAM and the SFR have different bus cycles. Ta

R8C/10 GroupRev.1.20 Jan 27, 2006 page 33 of 180REJ09B0019-0120• Maskable Interrupt: An interrupt which can be enabled (disabled) by the interrup

R8C/10 GroupRev.1.20 Jan 27, 2006 page 34 of 180REJ09B0019-012010.1.2 Software InterruptsA software interrupt occurs when executing certain inst

R8C/10 GroupRev.1.20 Jan 27, 2006 page 35 of 180REJ09B0019-012010.1.3 Hardware InterruptsHardware interrupts are classified into two types — spec

R8C/10 GroupRev.1.20 Jan 27, 2006 page 36 of 180REJ09B0019-0120Interrupt factor Vector addresses Remarks Reference Address (L) to address (H)Unde

R8C/10 GroupRev.1.20 Jan 27, 2006 page 37 of 180REJ09B0019-0120Table 10.2 Relocatable Vector TablesS o f t w a r e i n t e r r u p t n u m b

R8C/10 GroupRev.1.20 Jan 27, 2006 page 38 of 180REJ09B0019-012010.1.5 Interrupt ControlThe following describes how to enable/disable the maskable

R8C/10 GroupRev.1.20 Jan 27, 2006 page 39 of 180REJ09B0019-0120Figure 10.3 Interrupt Control RegistersS y m b o l A d d r e s sA f t e r r

A-1Table of ContentsSFR Page ReferenceChapter 1. Overview... 11.1 Applications ...

R8C/10 GroupRev.1.20 Jan 27, 2006 page 40 of 180REJ09B0019-0120• I FlagThe I flag enables or disables the maskable interrupt. Setting the I flag

R8C/10 GroupRev.1.20 Jan 27, 2006 page 41 of 180REJ09B0019-0120Figure 10.4 Time Required for Executing Interrupt Sequence• Interrupt SequenceAn

R8C/10 GroupRev.1.20 Jan 27, 2006 page 42 of 180REJ09B0019-0120Interrupt factors7Level that is set to IPLWatchdog timer, oscillation stop detecti

R8C/10 GroupRev.1.20 Jan 27, 2006 page 43 of 180REJ09B0019-0120• Saving RegistersIn the interrupt sequence, the FLG register and PC are saved to

R8C/10 GroupRev.1.20 Jan 27, 2006 page 44 of 180REJ09B0019-0120• Interrupt PriorityIf two or more interrupt requests are generated while executin

R8C/10 GroupRev.1.20 Jan 27, 2006 page 45 of 180REJ09B0019-0120Figure 10.9 Interrupts Priority Select CircuitInterruptrequestacceptedHighestLowe

R8C/10 GroupRev.1.20 Jan 27, 2006 page 46 of 180REJ09B0019-0120______10.2 INT Interrupt________10.2.1 INT0 Interrupt_______INT0 interrupt is trig

R8C/10 GroupRev.1.20 Jan 27, 2006 page 47 of 180REJ09B0019-0120_______10.2.2 INT0 Input Filter_______The INT0 input has a digital filter which ca

R8C/10 GroupRev.1.20 Jan 27, 2006 page 48 of 180REJ09B0019-0120______ ______10.2.3 INT1 Interrupt and INT2 Interrupt______ ______INT1 interrupts

R8C/10 GroupRev.1.20 Jan 27, 2006 page 49 of 180REJ09B0019-0120Figure 10.14 TCC0 Register and TCC1 Register______10.2.4 INT3 Interrupt_____ ____

A-26.3 CPU Clock and Peripheral Function Clock ... 236.3.1 CPU Clock...

R8C/10 GroupRev.1.20 Jan 27, 2006 page 50 of 180REJ09B0019-0120Key input interrupt requestPull-up transistorPull-up transistorPull-up transistorK

R8C/10 GroupRev.1.20 Jan 27, 2006 page 51 of 180REJ09B0019-012010.4 Address Match InterruptAn address match interrupt is generated immediately be

R8C/10 GroupRev.1.20 Jan 27, 2006 page 52 of 180REJ09B0019-0120Bit nameBit symbolSymbol Address After resetAIER 000916 XXXXXX002Address match int

R8C/10 Group 11. Watchdog TimerRev.1.20 Jan 27, 2006 page 53 of 180REJ09B0019-012011. Watchdog TimerThe watchdog timer is the function of detect

R8C/10 Group 11. Watchdog TimerRev.1.20 Jan 27, 2006 page 54 of 180REJ09B0019-0120Watchdog timer start registerSymbol Address After reset WDTS

R8C/10 GroupRev.1.20 Jan 27, 2006 page 55 of 180REJ09B0019-012012. TimersThe microcomputer has three 8-bit timers and one 16-bit timer. The three

R8C/10 GroupRev.1.20 Jan 27, 2006 page 56 of 180REJ09B0019-0120T X C K 1 t o T X C K 0= 0 02f1f8f32f2Toggle flip-flopP o l a r i t y s w i t

R8C/10 GroupRev.1.20 Jan 27, 2006 page 57 of 180REJ09B0019-0120Figure 12.3 PREX Register, TX Register, and TCSS RegisterB i t n a m eFunction

R8C/10 GroupRev.1.20 Jan 27, 2006 page 58 of 180REJ09B0019-012012.1.1 Timer ModeIn this mode, the timer counts an internally generated count sour

R8C/10 GroupRev.1.20 Jan 27, 2006 page 59 of 180REJ09B0019-012012.1.2 Pulse Output ModeIn this mode, the timer counts an internally generated cou

A-312.3.3 Programmable One-shot Generation Mode...8012.3.4 Programm

R8C/10 GroupRev.1.20 Jan 27, 2006 page 60 of 180REJ09B0019-012012.1.3 Event Counter Mode_____In this mode, the timer counts an external signal fe

R8C/10 GroupRev.1.20 Jan 27, 2006 page 61 of 180REJ09B0019-012012.1.4 Pulse Width Measurement Mode_____In this mode, the timer measures the pulse

R8C/10 GroupRev.1.20 Jan 27, 2006 page 62 of 180REJ09B0019-0120FFFF16n000016Counter contents (hex)n = high-level: the contents of TX register, lo

R8C/10 GroupRev.1.20 Jan 27, 2006 page 63 of 180REJ09B0019-012012.1.5 Pulse Period Measurement ModeIn this mode, the timer measures the pulse pe

R8C/10 GroupRev.1.20 Jan 27, 2006 page 64 of 180REJ09B0019-01200 F1 60 E1 60 E1 60 D1 60 C1 60B160A1609160 F1 60 E1 60 D1 60 11 60 01 60F160 E1 6

R8C/10 GroupRev.1.20 Jan 27, 2006 page 65 of 180REJ09B0019-012012.2 Timer YTimer Y is an 8-bit timer with an 8-bit prescaler and has two reload r

R8C/10 GroupRev.1.20 Jan 27, 2006 page 66 of 180REJ09B0019-0120T i m e r Y , Z o u t p u t c o n t r o l r e g i s t e r( 3 )Symbol Add

R8C/10 GroupRev.1.20 Jan 27, 2006 page 67 of 180REJ09B0019-0120Bit nameFunction Bit symbolT i m e r Y , Z w a v e f o r m o u t p u t c

R8C/10 GroupRev.1.20 Jan 27, 2006 page 68 of 180REJ09B0019-012012.2.1 Timer ModeIn this mode, the timer counts an internally generated count sour

R8C/10 GroupRev.1.20 Jan 27, 2006 page 69 of 180REJ09B0019-0120Figure 12.15 TYZMR Register and PUM Register in Timer ModeT i m e r Y , Z m

A-4Chapter 18. On-chip Debugger ... 16118.1 Address Match Interrupt ...

R8C/10 GroupRev.1.20 Jan 27, 2006 page 70 of 180REJ09B0019-012012.2.2 Programmable Waveform Generation ModeIn this mode, an signal output from th

R8C/10 GroupRev.1.20 Jan 27, 2006 page 71 of 180REJ09B0019-0120Figure 12.16 TYZMR Register and PUM Register in Programmable Waveform Generation

R8C/10 GroupRev.1.20 Jan 27, 2006 page 72 of 180REJ09B0019-0120CNTR1 pin output"H""L"IR bit in TYIC register"1"&quo

R8C/10 GroupRev.1.20 Jan 27, 2006 page 73 of 180REJ09B0019-0120TZSC registerf1f8T i m e r Y u n d e r f l o wf2T o g g l e f l i p - f l o

R8C/10 GroupRev.1.20 Jan 27, 2006 page 74 of 180REJ09B0019-0120Figure 12.20 PREZ Register, TZSC Register, TZPR Register, and TYZOC RegisterNOTES

R8C/10 GroupRev.1.20 Jan 27, 2006 page 75 of 180REJ09B0019-0120Figure 12.21 PUM Register and TCSS RegisterB i t n a m eF u n c t i o n Bit sy

R8C/10 GroupRev.1.20 Jan 27, 2006 page 76 of 180REJ09B0019-012012.3.1 Timer ModeIn this mode, the timer counts an internally generated count sour

R8C/10 GroupRev.1.20 Jan 27, 2006 page 77 of 180REJ09B0019-0120Figure 12.22 TYZMR Register and PUM Register in Timer ModeBit nameFunction Bit sy

R8C/10 GroupRev.1.20 Jan 27, 2006 page 78 of 180REJ09B0019-012012.3.2 Programmable Waveform Generation ModeIn this mode, an signal output from th

R8C/10 GroupRev.1.20 Jan 27, 2006 page 79 of 180REJ09B0019-0120Figure 12.23 TYZMR Register and PUM Register in Programmable Waveform Generation

B-1SFR Page ReferenceW a t c h d o g t i m e r s t a r t r e g i s t e rW D T S5 4W a t c h d o g t i m e r c o n t r o l r e g i s t e rW

R8C/10 GroupRev.1.20 Jan 27, 2006 page 80 of 180REJ09B0019-012012.3.3 Programmable One-shot Generation ModeIn this mode, upon program command or

R8C/10 GroupRev.1.20 Jan 27, 2006 page 81 of 180REJ09B0019-0120Figure 12.24 TYZMR Register and PUM Register in Programmable One-shot Generation

R8C/10 GroupRev.1.20 Jan 27, 2006 page 82 of 180REJ09B0019-0120Figure 12.25 Operation Example in Programmable One-shot Generation ModeCount sour

R8C/10 GroupRev.1.20 Jan 27, 2006 page 83 of 180REJ09B0019-012012.3.4 Programmable Wait One-shot Generation ModeIn this mode, upon program or ext

R8C/10 GroupRev.1.20 Jan 27, 2006 page 84 of 180REJ09B0019-0120Figure 12.26 TYZMR Register and PUM Register in Programmable Wait One-shot Genera

R8C/10 GroupRev.1.20 Jan 27, 2006 page 85 of 180REJ09B0019-0120T ZO U T p i n o u t p u tThe above applies to the following conditions;PREZ=01

R8C/10 GroupRev.1.20 Jan 27, 2006 page 86 of 180REJ09B0019-012012.4 Timer CTimer C is a 16-bit free-running timer. Figure 12.28 shows a block di

R8C/10 GroupRev.1.20 Jan 27, 2006 page 87 of 180REJ09B0019-0120Symbol Address After reset TC 009116-009016 000016RW Internal count source is coun

R8C/10 GroupRev.1.20 Jan 27, 2006 page 88 of 180REJ09B0019-0120Counter contents (hex)TCC00 bit in TCC0 registerMeasurement pulse(TCIN pin input)T

R8C/10 Group 13. Serial InterfaceRev.1.20 Jan 27, 2006 page 89 of 180REJ09B0019-012013. Serial InterfaceSerial interface is configured with two