Renesas R8C/Tiny Series Manuál stáhnout pdf (Strana 17)

R8C/10 Group 2. Central Processing Unit (CPU)

Rev.1.20 Jan 27, 2006 page 7 of 180

REJ09B0019-0120

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB

comprise a register bank. Two sets of register banks are provided.

2.1 Data Registers (R0, R1, R2 and R3)

R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The

R0 can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data

registers. The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be

used as a 32-bit data register (R2R0). The same applies to R3R1 as R2R0.

Data registers

(1)

Address registers

(1)

Frame base registers

(1)

Program counter

Interrupt table register

User stack pointer

Interrupt stack pointer

Static base register

Flag register

(

)

b7 b

ISP

CDZSBOIU

(

)

R1H (high-order of R1)

R1L (high-order of R1)

b19

FLG

b7 b8

Reserved bit

Carry flag

Debug flag

Zero flag

Sign flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved bit

Processor interrupt priority level

The 4-high order bits of INTB are INTBH and

the 16-low bits of INTB are INTBL.

Figure 2.1 CPU Register

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 ... 198 199

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